diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-11-19 16:09:23 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-11-23 11:43:27 +0300 |
| commit | 89ad953e1e727640e85beb82db3c71d45a59b177 (patch) | |
| tree | 0fd44ab555075e08efaea378a451325ef0556620 /drivers/pinctrl/renesas | |
| parent | d4aac7d439c2d9307cb5137fc285464a36978107 (diff) | |
| download | linux-89ad953e1e727640e85beb82db3c71d45a59b177.tar.xz | |
pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions
Add pins, groups and functions for QSPIO[01].
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201119130926.25692-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl/renesas')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a77990.c | 75 |
1 files changed, 73 insertions, 2 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index a51c1e684439..0a32e3c317c1 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2810,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + /* QSPI0_IO2, QSPI0_IO3 */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* QSPI1_IO2, QSPI1_IO3 */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -3762,7 +3813,7 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[247]; + struct sh_pfc_pin_group common[253]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[21]; #endif @@ -3910,6 +3961,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_ctrl_a), @@ -4313,6 +4370,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -4467,7 +4536,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[47]; + struct sh_pfc_function common[49]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_function automotive[4]; #endif @@ -4504,6 +4573,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), |