diff options
| author | Jes Sorensen <Jes.Sorensen@redhat.com> | 2016-04-14 21:58:56 +0300 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2016-04-15 21:36:37 +0300 |
| commit | bd8fe40cc4f30f3f0982345135d97a676d1d3652 (patch) | |
| tree | d76b1e808fd45d5fa43e75587eb0843c90ba7449 /drivers/net | |
| parent | 9068308ad185a3c2c5d7beb77146b6df7b96b9c6 (diff) | |
| download | linux-bd8fe40cc4f30f3f0982345135d97a676d1d3652.tar.xz | |
rtl8xxxu: Use descriptive bits for setting RX paths for 1T2R parts
This reduce the use of magic values a little.
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c | 4 | ||||
| -rw-r--r-- | drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 4 |
2 files changed, 7 insertions, 1 deletions
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c index d0330a8f32fb..3c45ad0bdbca 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c @@ -3814,8 +3814,10 @@ static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); + val32 &= ~CCK0_AFE_RX_MASK; val32 &= 0x00ffffff; - val32 |= 0x45000000; + val32 |= 0x40000000; + val32 |= CCK0_AFE_RX_ANT_B; rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h index a2cff2273e72..e7709a5bcb3a 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h @@ -882,6 +882,10 @@ #define CCK0_SIDEBAND BIT(4) #define REG_CCK0_AFE_SETTING 0x0a04 +#define CCK0_AFE_RX_MASK 0x0f000000 +#define CCK0_AFE_RX_ANT_AB BIT(24) +#define CCK0_AFE_RX_ANT_A 0 +#define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) #define REG_CONFIG_ANT_A 0x0b68 #define REG_CONFIG_ANT_B 0x0b6c |