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| author | David S. Miller <davem@davemloft.net> | 2020-04-20 21:12:29 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-04-20 21:12:29 +0300 |
| commit | ad3df63723a3fab65daaaf2daaa1a196659bb8e3 (patch) | |
| tree | 1c2d917e90671a5e05da557104148828fbdfb3fa /drivers/net | |
| parent | 6d92797716003a462bd75bbda3740718ce54bcdd (diff) | |
| parent | 109f0cf23b094b0b780a22ce1c9ea267ebcd3974 (diff) | |
| download | linux-ad3df63723a3fab65daaaf2daaa1a196659bb8e3.tar.xz | |
Merge branch 'net-phy-realtek-move-PHY-resume-delay-from-MAC-to-PHY-driver'
Heiner Kallweit says:
====================
net: phy: realtek: move PHY resume delay from MAC to PHY driver
Internal PHY's from RTL8168h up may not be instantly ready after calling
genphy_resume(). So far r8169 network driver adds the needed delay, but
better handle this in the PHY driver. The network driver may miss other
places where the PHY is resumed.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/realtek/r8169_main.c | 2 | ||||
| -rw-r--r-- | drivers/net/phy/realtek.c | 15 |
2 files changed, 13 insertions, 4 deletions
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index a8696d958cd1..1bc415d00cb8 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -2391,8 +2391,6 @@ static void rtl_pll_power_up(struct rtl8169_private *tp) } phy_resume(tp->phydev); - /* give MAC/PHY some time to resume */ - msleep(20); } static void rtl_init_rxcfg(struct rtl8169_private *tp) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 2d99e9de6ee1..c7229d022a27 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -11,6 +11,7 @@ #include <linux/bitops.h> #include <linux/phy.h> #include <linux/module.h> +#include <linux/delay.h> #define RTL821x_PHYSR 0x11 #define RTL821x_PHYSR_DUPLEX BIT(13) @@ -526,6 +527,16 @@ static int rtl8125_match_phy_device(struct phy_device *phydev) rtlgen_supports_2_5gbps(phydev); } +static int rtlgen_resume(struct phy_device *phydev) +{ + int ret = genphy_resume(phydev); + + /* Internal PHY's from RTL8168h up may not be instantly ready */ + msleep(20); + + return ret; +} + static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), @@ -609,7 +620,7 @@ static struct phy_driver realtek_drvs[] = { .match_phy_device = rtlgen_match_phy_device, .read_status = rtlgen_read_status, .suspend = genphy_suspend, - .resume = genphy_resume, + .resume = rtlgen_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, .read_mmd = rtlgen_read_mmd, @@ -621,7 +632,7 @@ static struct phy_driver realtek_drvs[] = { .config_aneg = rtl8125_config_aneg, .read_status = rtl8125_read_status, .suspend = genphy_suspend, - .resume = genphy_resume, + .resume = rtlgen_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, .read_mmd = rtl8125_read_mmd, |