diff options
author | Felix Fietkau <nbd@nbd.name> | 2019-02-25 19:25:38 +0300 |
---|---|---|
committer | Felix Fietkau <nbd@nbd.name> | 2019-02-26 12:28:19 +0300 |
commit | 4606a26c0c51d23401a00d787aa61e508f3e14a7 (patch) | |
tree | aae009235a79a5032217e4104922aeb76c4bcd17 /drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c | |
parent | 72e5d479b8de4a3b3cbc01f9fcc4a6936f82414f (diff) | |
download | linux-4606a26c0c51d23401a00d787aa61e508f3e14a7.tar.xz |
mt76: mt76x02: fix ED/CCA enabling/disabling
ED/CCA needs to be disable before stopping the MAC to avoid hangs from tx
being blocked. It must only be enabled again after the MAC has been started
again.
In many places this wasn't done properly, so fix this by always clearing
the relevant ED/CCA bits in mt76x2_mac_stop and set it up again after
channel change or calibration is done
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c')
-rw-r--r-- | drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c index 97ec575699d0..cc1aebcb0696 100644 --- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c +++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c @@ -74,6 +74,7 @@ mt76x2_phy_channel_calibrate(struct mt76x02_dev *dev, bool mac_stopped) mt76x2_mac_resume(dev); mt76x2_apply_gain_adj(dev); + mt76x02_edcca_init(dev, true); dev->cal.channel_cal_done = true; } @@ -240,10 +241,8 @@ int mt76x2_phy_set_channel(struct mt76x02_dev *dev, mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F); - if (scan) { - mt76x02_edcca_init(dev, false); + if (scan) return 0; - } mt76x2_phy_channel_calibrate(dev, true); mt76x02_init_agc_gain(dev); @@ -256,8 +255,6 @@ int mt76x2_phy_set_channel(struct mt76x02_dev *dev, 0x38); } - mt76x02_edcca_init(dev, true); - ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work, MT_CALIBRATE_INTERVAL); |