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authorJoao Pinto <Joao.Pinto@synopsys.com>2017-03-10 21:24:55 +0300
committerDavid S. Miller <davem@davemloft.net>2017-03-13 09:41:03 +0300
commitd43042f4da3e1c2e4ccac3b1d9153cb0798533a4 (patch)
treeb17835d1c4ebd5d2a66ad8fe1cde16f7c0328eb5 /drivers/net/ethernet/stmicro/stmmac/dwmac4.h
parent4f6046f5872c7db6a152b923cee21c37a04d56b8 (diff)
downloadlinux-d43042f4da3e1c2e4ccac3b1d9153cb0798533a4.tar.xz
net: stmmac: mapping mtl rx to dma channel
This patch adds the functionality of RX queue to dma channel mapping based on configuration. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac4.h')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac4.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index 89824fe484f6..773f25b8e403 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -177,6 +177,13 @@ enum power_event {
#define MTL_INT_STATUS 0x00000c20
#define MTL_INT_Q0 BIT(0)
+#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
+#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
+#define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
+#define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
+#define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
+#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
+
#define MTL_CHAN_BASE_ADDR 0x00000d00
#define MTL_CHAN_BASE_OFFSET 0x40
#define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \