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author | David S. Miller <davem@davemloft.net> | 2020-06-25 00:33:17 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2020-06-25 00:33:17 +0300 |
commit | b430081b0c9ed2065ca5250e8cffc5027261162d (patch) | |
tree | cb22728170f57906f92d708fdb9e505fa0a4ea14 /drivers/net/ethernet/microchip | |
parent | 7b0cc34ac4795f5e1b7c586f136866f25e9b5ae5 (diff) | |
parent | 15324652f61287e2e640ca47f2a044df6cccf4b3 (diff) | |
download | linux-b430081b0c9ed2065ca5250e8cffc5027261162d.tar.xz |
Merge branch 'net-phy-mscc-PHC-and-timestamping-support'
Antoine Tenart says:
====================
net: phy: mscc: PHC and timestamping support
This series aims at adding support for PHC and timestamping operations
in the MSCC PHY driver, for the VSC858x and VSC8575. Those PHYs are
capable of timestamping in 1-step and 2-step for both L2 and L4 traffic.
As of this series, only IPv4 support was implemented when using L4 mode.
This is because of an hardware limitation which prevents us for
supporting both IPv4 and IPv6 at the same time. Implementing support for
IPv6 should be quite easy (I do have the modifications needed for the
hardware configuration) but I did not see a way to retrieve this
information in hwtstamp(). What would you suggest?
Those PHYs are distributed in hardware packages containing multiple
times the PHY. The VSC8584 for example is composed of 4 PHYs. With
hardware packages, parts of the logic is usually common and one of the
PHY has to be used for some parts of the initialization. Following this
logic, the 1588 blocks of those PHYs are shared between two PHYs and
accessing the registers has to be done using the "base" PHY of the
group. This is handled thanks to helpers in the PTP code (and locks).
We also need the MDIO bus lock while performing a single read or write
to the 1588 registers as the read/write are composed of multiple MDIO
transactions (and we don't want other threads updating the page).
To get and set the PHC time, a GPIO has to be used and changes are only
retrieved or committed when on a rising edge. The same GPIO is shared by
all PHYs, so the granularity of the lock protecting it has to be
different from the ones protecting the 1588 registers (the VSC8584 PHY
has 2 1588 blocks, and a single load/save pin).
Patch 1 extends the recently added helpers to share information between
PHYs of the same hardware package; to allow having part of the probe to
be shared (in addition to the already supported init part). This will be
used when adding support for PHC/TS to initialize locks.
Patches 2 and 3 are mostly cosmetic.
Patch 4 takes into account the 1588 block in the MACsec initialization,
to allow having both the MACsec and 1588 blocks initialized on a running
system.
Patches 5 and 6 add support for PHC and timestamping operations in the
MSCC driver. An initialization of the 1588 block (plus all the registers
definition; and helpers) is added first; and then comes a patch to
implement the PHC and timestamping API.
Patches 7 and 8 add the required hardware description for device trees,
to be able to use the load/save GPIO pin on the PCB120 board.
To use this on a PCB120 board, two other series are needed and have
already been sent upstream (one is merged). There are no dependency
between all those series.
Since v3:
- Fixed a SKB leak.
- Removed ts_lock from the init, as TS and PHC operations aren't
registered at this time.
- Refectored the ts_base_addr/phy intialization.
- Cleaned up the ingr/egr latencies definitons.
- Fixed a comment about locking and the shared GPIO.
- A few cosmetic fixes.
Since v2:
- Removed explicit inlines from .c files.
- Fixed three warnings.
Since v1:
- Removed checks in rxtstamp/txtstamp as skb cannot be NULL here.
- Reworked get_ptp_header_rx/get_ptp_header.
- Reworked the locking logic between the PHC and timestamping
operations.
- Fixed a compilation issue on x86 reported by Jakub.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/microchip')
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