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author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2021-07-19 04:56:58 +0300 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2021-07-19 04:56:58 +0300 |
commit | 320424c7d44f54c18df9812fd7c45f6963524002 (patch) | |
tree | 5853aff866a321d476f5e4f2a3de5b5e90408580 /drivers/mtd/nand/raw/fsmc_nand.c | |
parent | f8f84af5da9ee04ef1d271528656dac42a090d00 (diff) | |
parent | 62fb9874f5da54fdb243003b386128037319b219 (diff) | |
download | linux-320424c7d44f54c18df9812fd7c45f6963524002.tar.xz |
Merge tag 'v5.13' into next
Sync up with the mainline to get the latest parport API.
Diffstat (limited to 'drivers/mtd/nand/raw/fsmc_nand.c')
-rw-r--r-- | drivers/mtd/nand/raw/fsmc_nand.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index 0101c0fab50a..a3e66155ae40 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -25,6 +25,7 @@ #include <linux/sched.h> #include <linux/types.h> #include <linux/mtd/mtd.h> +#include <linux/mtd/nand-ecc-sw-hamming.h> #include <linux/mtd/rawnand.h> #include <linux/platform_device.h> #include <linux/of.h> @@ -432,6 +433,15 @@ static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data, return 0; } +static int fsmc_correct_ecc1(struct nand_chip *chip, + unsigned char *buf, + unsigned char *read_ecc, + unsigned char *calc_ecc) +{ + return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc, + chip->ecc.size, false); +} + /* Count the number of 0's in buff upto a max of max_bits */ static int count_written_bits(u8 *buff, int size, int max_bits) { @@ -917,7 +927,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand) case NAND_ECC_ENGINE_TYPE_ON_HOST: dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); nand->ecc.calculate = fsmc_read_hwecc_ecc1; - nand->ecc.correct = rawnand_sw_hamming_correct; + nand->ecc.correct = fsmc_correct_ecc1; nand->ecc.hwctl = fsmc_enable_hwecc; nand->ecc.bytes = 3; nand->ecc.strength = 1; @@ -930,6 +940,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand) "Using 4-bit SW BCH ECC scheme\n"); break; } + break; case NAND_ECC_ENGINE_TYPE_ON_DIE: break; @@ -1077,11 +1088,13 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) host->read_dma_chan = dma_request_channel(mask, filter, NULL); if (!host->read_dma_chan) { dev_err(&pdev->dev, "Unable to get read dma channel\n"); + ret = -ENODEV; goto disable_clk; } host->write_dma_chan = dma_request_channel(mask, filter, NULL); if (!host->write_dma_chan) { dev_err(&pdev->dev, "Unable to get write dma channel\n"); + ret = -ENODEV; goto release_dma_read_chan; } } |