diff options
| author | Koby Elbaz <kelbaz@habana.ai> | 2021-05-12 18:05:46 +0300 |
|---|---|---|
| committer | Oded Gabbay <ogabbay@kernel.org> | 2021-06-18 15:23:40 +0300 |
| commit | e591a49cb585ca76d4f9aad2e9635ec7e6a4fb23 (patch) | |
| tree | 41def68404d2e708a3957960a4d7405e7c902557 /drivers/misc/habanalabs/include | |
| parent | 190ec49710a9fe0d5e9e36fe1a2fa864c048484f (diff) | |
| download | linux-e591a49cb585ca76d4f9aad2e9635ec7e6a4fb23.tar.xz | |
habanalabs/gaudi: read GIC sts after FW is loaded
Reading of GIC privileged status will be done after F/W is loaded,
because privileged GIC capability is only available with the correct
ARMCP version, and after it's loaded.
Such versions necessarily support COMMS, so GIC alternatives (SP regs)
will be read directly from dynamic regs.
As well, initiation of DMA QMANs will occur after F/W is loaded
since it depends on GIC configuration.
In case F/W isn't loaded there's no problem since either way
there won't be any GIC IRQ handling.
Signed-off-by: Koby Elbaz <kelbaz@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/include')
| -rw-r--r-- | drivers/misc/habanalabs/include/common/hl_boot_if.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h index e9d86673109c..9266c44d8c6c 100644 --- a/drivers/misc/habanalabs/include/common/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h @@ -195,7 +195,7 @@ * previleged entity. FW sets this status * bit for host. If this bit is set then * GIC can not be accessed from host. - * Initialized in: preboot + * Initialized in: armcpd * * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. * This is a main indication that the @@ -299,7 +299,13 @@ struct cpu_dyn_regs { __le32 hw_state; __le32 kmd_msg_to_cpu; __le32 cpu_cmd_status_to_host; - __le32 reserved1[32]; /* reserve for future use */ + __le32 gic_host_irq_ctrl; + __le32 gic_tpc_qm_irq_ctrl; + __le32 gic_mme_qm_irq_ctrl; + __le32 gic_dma_qm_irq_ctrl; + __le32 gic_nic_qm_irq_ctrl; + __le32 gic_dma_core_irq_ctrl; + __le32 reserved1[26]; /* reserve for future use */ }; /* TODO: remove the desc magic after the code is updated to use message */ |