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| author | Will Deacon <will.deacon@arm.com> | 2015-08-04 20:52:09 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-08-04 20:52:09 +0300 |
| commit | 04b8637be92f284409651088f3856f4290a931d8 (patch) | |
| tree | aee6f9d734c0893139664f38d6438e3897dd568b /drivers/irqchip/irq-tb10x.c | |
| parent | 7f08a414f29e7daea661d03231998625257ed3f1 (diff) | |
| download | linux-04b8637be92f284409651088f3856f4290a931d8.tar.xz | |
arm64: alternatives: ensure secondary CPUs execute ISB after patching
In order to guarantee that the patched instruction stream is visible to
a CPU, that CPU must execute an isb instruction after any related cache
maintenance has completed.
The instruction patching routines in kernel/insn.c get this right for
things like jump labels and ftrace, but the alternatives patching omits
it entirely leaving secondary cores in a potential limbo between the old
and the new code.
This patch adds an isb following the secondary polling loop in the
altenatives patching.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/irqchip/irq-tb10x.c')
0 files changed, 0 insertions, 0 deletions