diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2017-12-21 23:23:30 +0300 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2018-02-14 19:17:02 +0300 |
| commit | 3e5907a17fe4aa42d32015482132475e2b39ad50 (patch) | |
| tree | 1a322cca3183d1cf3f8b0d4e02543f4a88deb070 /drivers/gpu/drm/rcar-du/rcar_lvds_regs.h | |
| parent | 9ff3e797e4d6faf4cbe94f10572cfc8b3ea30109 (diff) | |
| download | linux-3e5907a17fe4aa42d32015482132475e2b39ad50.tar.xz | |
drm: rcar-du: lvds: Fix LVDCR1 for R-Car gen3
The LVDCR1 register for the R-Car gen3 SoCs was documented as having the
layout different from the gen2 SoCs in the early R-Car gen3 manuals but
since v0.52 the LVDCR1 layout is described as being the same as on the gen2
SoCs; the old CHn control values are said to be prohibited now (and there
seems to be no valid output signal when they are used).
Fixes: 6bc2e15cf21c ("drm: rcar-du: lvds: Add R-Car Gen3 support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_lvds_regs.h')
| -rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_lvds_regs.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h index d7d294ba2dbe..2896835ca7e9 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h @@ -26,10 +26,8 @@ #define LVDCR1 0x0004 #define LVDCR1_CKSEL (1 << 15) /* Gen2 only */ -#define LVDCR1_CHSTBY_GEN2(n) (3 << (2 + (n) * 2)) /* Gen2 only */ -#define LVDCR1_CHSTBY_GEN3(n) (1 << (2 + (n) * 2)) /* Gen3 only */ -#define LVDCR1_CLKSTBY_GEN2 (3 << 0) /* Gen2 only */ -#define LVDCR1_CLKSTBY_GEN3 (1 << 0) /* Gen3 only */ +#define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2)) +#define LVDCR1_CLKSTBY (3 << 0) #define LVDPLLCR 0x0008 #define LVDPLLCR_CEEN (1 << 14) |