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| author | Wangyan Wang <wangyan.wang@mediatek.com> | 2019-04-09 09:53:06 +0300 |
|---|---|---|
| committer | CK Hu <ck.hu@mediatek.com> | 2019-04-09 12:46:54 +0300 |
| commit | 321b628e6f5a3af999f75eadd373adbcb8b4cb1f (patch) | |
| tree | f08e6986ea2112b2e98150e66d6d9465d288e315 /drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | |
| parent | 0c24613cda163dedfa229afc8eff6072e57fac8d (diff) | |
| download | linux-321b628e6f5a3af999f75eadd373adbcb8b4cb1f.tar.xz | |
drm/mediatek: make implementation of recalc_rate() for MT2701 hdmi phy
Recalculate the rate of this clock, by querying hardware to
make implementation of recalc_rate() to match the definition.
Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'drivers/gpu/drm/mediatek/mtk_hdmi_phy.c')
| -rw-r--r-- | drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c index 4ef9c57ffd44..efc400ebbb90 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c @@ -29,14 +29,6 @@ long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, return rate; } -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); - - return hdmi_phy->pll_rate; -} - void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, u32 bits) { |