diff options
| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-04-27 15:44:22 +0300 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-04-29 09:57:36 +0300 |
| commit | 53d9872511c4911616ae39f59d97afb62510d81e (patch) | |
| tree | 100a26b4221ce5c21a238f404b24f5b75ed969a1 /drivers/gpu/drm/i915/intel_hdmi.c | |
| parent | 204970b5cf8a3d3367b346df0ec6f56279ad8fca (diff) | |
| download | linux-53d9872511c4911616ae39f59d97afb62510d81e.tar.xz | |
drm/i915: Unduplicate VLV signal level code
The logic for setting signal levels is used for both HDMI and DP with
small variations. But it is similar enough to put behind a function
called from the encoders.
v2: Remove unrelated MST changes due to rebase fumble. (Jim Bride)
Fix typo in the commit message. (Jim Bride)
v3: Really fix the typo. (Jim)
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-8-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index ed7889e218e9..5c044ced6731 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1609,21 +1609,15 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) val |= 0x001000c4; vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); - /* HDMI 1.0V-2dB */ - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); - vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); - /* Program lane clock */ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); mutex_unlock(&dev_priv->sb_lock); + /* HDMI 1.0V-2dB */ + vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, + 0x2b247878); + intel_hdmi->set_infoframes(&encoder->base, intel_crtc->config->has_hdmi_sink, adjusted_mode); |