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authorSatheeshakrishna M <satheeshakrishna.m@intel.com>2014-08-22 08:19:06 +0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-04-16 12:29:05 +0300
commit1ab23380f8b990ad865349040ec14c3ebe3a09c5 (patch)
tree0862b833474b5e9e86a743667a51aa4f5930715d /drivers/gpu/drm/i915/intel_ddi.c
parent535afa2e9e3c1867460d6981d879b04d8b2b9ab3 (diff)
downloadlinux-1ab23380f8b990ad865349040ec14c3ebe3a09c5.tar.xz
drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9
PORT_CLK_SEL programming is needed only on HSW/BDW. v2: - don't program PORT_CLK_SEL from mst encoders either (imre) v3: - fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien) Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 24ecb486465b..f98a403c6625 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1567,7 +1567,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
I915_WRITE(DPLL_CTRL2, val);
- } else {
+ } else if (INTEL_INFO(dev)->gen < 9) {
WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
}
@@ -1626,7 +1626,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
if (IS_SKYLAKE(dev))
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port)));
- else
+ else if (INTEL_INFO(dev)->gen < 9)
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}