diff options
| author | Andrzej Hajda <a.hajda@samsung.com> | 2017-02-01 10:47:47 +0300 |
|---|---|---|
| committer | Archit Taneja <architt@codeaurora.org> | 2017-02-02 12:45:29 +0300 |
| commit | bf1722cab55a32a7a18c0155034351084bac59fa (patch) | |
| tree | e29e561c1685b4f8c461b30ae83cabd0d41f90fc /drivers/gpu/drm/bridge/sil-sii8620.h | |
| parent | be1cd6fe205806fbbcf59061d7b64759b160ca31 (diff) | |
| download | linux-bf1722cab55a32a7a18c0155034351084bac59fa.tar.xz | |
drm/bridge/sii8620: rewrite hdmi start sequence
MHL3 protocol requires registry adjustments depending on chosen video mode.
Necessary information is gathered in mode_fixup callback. In case of HDMI
video modes driver should also send special AVI and MHL3 infoframes.
The patch introduces generic helpers for handling MHL3 infoframes, in
case of appearance of other users of MHL3 infoframes these function can
be moved to common library.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-21-git-send-email-a.hajda@samsung.com
Diffstat (limited to 'drivers/gpu/drm/bridge/sil-sii8620.h')
| -rw-r--r-- | drivers/gpu/drm/bridge/sil-sii8620.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.h b/drivers/gpu/drm/bridge/sil-sii8620.h index 683213acc756..613943aaf90d 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.h +++ b/drivers/gpu/drm/bridge/sil-sii8620.h @@ -1084,10 +1084,17 @@ /* TPI Info Frame Select, default value: 0x00 */ #define REG_TPI_INFO_FSEL 0x06bf -#define BIT_TPI_INFO_FSEL_TPI_INFO_EN BIT(7) -#define BIT_TPI_INFO_FSEL_TPI_INFO_RPT BIT(6) -#define BIT_TPI_INFO_FSEL_TPI_INFO_READ_FLAG BIT(5) -#define MSK_TPI_INFO_FSEL_TPI_INFO_SEL 0x07 +#define BIT_TPI_INFO_FSEL_EN BIT(7) +#define BIT_TPI_INFO_FSEL_RPT BIT(6) +#define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5) +#define MSK_TPI_INFO_FSEL_PKT 0x07 +#define VAL_TPI_INFO_FSEL_AVI 0x00 +#define VAL_TPI_INFO_FSEL_SPD 0x01 +#define VAL_TPI_INFO_FSEL_AUD 0x02 +#define VAL_TPI_INFO_FSEL_MPG 0x03 +#define VAL_TPI_INFO_FSEL_GEN 0x04 +#define VAL_TPI_INFO_FSEL_GEN2 0x05 +#define VAL_TPI_INFO_FSEL_VSI 0x06 /* TPI Info Byte #0, default value: 0x00 */ #define REG_TPI_INFO_B0 0x06c0 |