diff options
author | Dave Airlie <airlied@redhat.com> | 2017-09-29 04:12:30 +0300 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-29 19:24:37 +0300 |
commit | ce27643cc0f56f7a70de17c2ef54541ad4252c1a (patch) | |
tree | bc54458eb718e90141c6a56c5258c8b01fecd747 /drivers/gpu/drm/amd/powerplay/inc | |
parent | d81a2209498b6349a33f8741ca5a062dde84c043 (diff) | |
download | linux-ce27643cc0f56f7a70de17c2ef54541ad4252c1a.tar.xz |
amdgpu/pp: use array_size to size the pwrvirus tables.
This avoids fragile hardcoding of array size.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h | 5 |
2 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h index 243de293a3ef..e202e567faf4 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h +++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h @@ -35,8 +35,7 @@ struct PWR_Command_Table }; typedef struct PWR_Command_Table PWR_Command_Table; -#define PWR_VIRUS_TABLE_SIZE 10243 -static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] = +static const PWR_Command_Table PwrVirusTable[] = { { 0x100100b6, mmPCIE_INDEX }, { 0x00000000, mmPCIE_DATA }, diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h index 76039860580d..8edd3e7860b7 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h @@ -36,10 +36,7 @@ struct PWR_Command_Table { typedef struct PWR_Command_Table PWR_Command_Table; - -#define PWR_VIRUS_TABLE_SIZE 10031 - -static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = { +static const PWR_Command_Table pwr_virus_table[] = { { 0x00000000, mmRLC_CNTL }, { 0x00000002, mmRLC_SRM_CNTL }, { 0x15000000, mmCP_ME_CNTL }, |