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author | Dave Airlie <airlied@redhat.com> | 2018-03-21 04:46:05 +0300 |
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committer | Dave Airlie <airlied@redhat.com> | 2018-03-21 04:46:05 +0300 |
commit | 287d2ac36b6f2830ea4ef66c110abc0f47a9a658 (patch) | |
tree | 04214f156461a95c2f7ca5a8821063cad7fc515e /drivers/gpu/drm/amd/include/soc15_ih_clientid.h | |
parent | 963976cfe9c54d4d9e725e61c90c47a4af6b5ea2 (diff) | |
parent | 6da2b9332c572fcda94de9631f8fa514f574388a (diff) | |
download | linux-287d2ac36b6f2830ea4ef66c110abc0f47a9a658.tar.xz |
Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next
- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes
* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
drm/amd/display: fix dereferencing possible ERR_PTR()
drm/amd/display: Refine disable VGA
drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
drm/radeon: Don't turn off DP sink when disconnected
drm/amd/pp: Rename file name cz_* to smu8_*
drm/amd/pp: Replace function/struct name cz_* with smu8_*
drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
drm/amd/pp: Remove dead header file pp_asicblocks.h
drm/amd/pp: Delete dead code on cz_clockpowergating.c
drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
drm/amdgpu: Remove wrapper layer of smu ip functions
drm/amdgpu: Don't compared ip_block_type with ip_block_index
drm/amdgpu: Plus NULL function pointer check
drm/amd/pp: Move helper functions to smu_help.c
drm/amd/pp: Replace rv_* with smu10_*
drm/amd/pp: Fix function parameter not correct
drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
...
Diffstat (limited to 'drivers/gpu/drm/amd/include/soc15_ih_clientid.h')
-rw-r--r-- | drivers/gpu/drm/amd/include/soc15_ih_clientid.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h new file mode 100644 index 000000000000..a12d4f27cfa4 --- /dev/null +++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h @@ -0,0 +1,70 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SOC15_IH_CLIENTID_H__ +#define __SOC15_IH_CLIENTID_H__ + + /* + * vega10+ IH clients + */ +enum soc15_ih_clientid { + SOC15_IH_CLIENTID_IH = 0x00, + SOC15_IH_CLIENTID_ACP = 0x01, + SOC15_IH_CLIENTID_ATHUB = 0x02, + SOC15_IH_CLIENTID_BIF = 0x03, + SOC15_IH_CLIENTID_DCE = 0x04, + SOC15_IH_CLIENTID_ISP = 0x05, + SOC15_IH_CLIENTID_PCIE0 = 0x06, + SOC15_IH_CLIENTID_RLC = 0x07, + SOC15_IH_CLIENTID_SDMA0 = 0x08, + SOC15_IH_CLIENTID_SDMA1 = 0x09, + SOC15_IH_CLIENTID_SE0SH = 0x0a, + SOC15_IH_CLIENTID_SE1SH = 0x0b, + SOC15_IH_CLIENTID_SE2SH = 0x0c, + SOC15_IH_CLIENTID_SE3SH = 0x0d, + SOC15_IH_CLIENTID_SYSHUB = 0x0e, + SOC15_IH_CLIENTID_THM = 0x0f, + SOC15_IH_CLIENTID_UVD = 0x10, + SOC15_IH_CLIENTID_VCE0 = 0x11, + SOC15_IH_CLIENTID_VMC = 0x12, + SOC15_IH_CLIENTID_XDMA = 0x13, + SOC15_IH_CLIENTID_GRBM_CP = 0x14, + SOC15_IH_CLIENTID_ATS = 0x15, + SOC15_IH_CLIENTID_ROM_SMUIO = 0x16, + SOC15_IH_CLIENTID_DF = 0x17, + SOC15_IH_CLIENTID_VCE1 = 0x18, + SOC15_IH_CLIENTID_PWR = 0x19, + SOC15_IH_CLIENTID_UTCL2 = 0x1b, + SOC15_IH_CLIENTID_EA = 0x1c, + SOC15_IH_CLIENTID_UTCL2LOG = 0x1d, + SOC15_IH_CLIENTID_MP0 = 0x1e, + SOC15_IH_CLIENTID_MP1 = 0x1f, + + SOC15_IH_CLIENTID_MAX, + + SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD +}; + +#endif + + |