drm/amd/display: dce120 to dce ipp refactor

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6 files changed, 33 insertions, 517 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile
index 3c6b3fa98ddc..826c12ee368c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile
@@ -4,7 +4,6 @@
 
 
 DCE120 = dce120_resource.o dce120_timing_generator.o \
-dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \
 dce120_mem_input.o dce120_hw_sequencer.o
 
 AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120))
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
deleted file mode 100644
index f4505690e01a..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/logger_interface.h"
-
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
-
-#include "dce120_ipp.h"
-
-static const struct ipp_funcs funcs = {
-		.ipp_cursor_set_attributes = dce120_ipp_cursor_set_attributes,
-		.ipp_cursor_set_position = dce120_ipp_cursor_set_position,
-		.ipp_program_prescale = dce120_ipp_program_prescale,
-		.ipp_program_input_lut = dce120_ipp_program_input_lut,
-		.ipp_set_degamma = dce120_ipp_set_degamma,
-};
-
-bool dce120_ipp_construct(
-	struct dce110_ipp *ipp,
-	struct dc_context *ctx,
-	uint32_t inst,
-	const struct dce110_ipp_reg_offsets *offset)
-{
-	if (!dce110_ipp_construct(ipp, ctx, inst, offset)) {
-		ASSERT_CRITICAL(false);
-		return false;
-	}
-
-	ipp->base.funcs = &funcs;
-
-	return true;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
deleted file mode 100644
index 7f645fde7064..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_IPP_DCE120_H__
-#define __DC_IPP_DCE120_H__
-
-#include "ipp.h"
-#include "../dce110/dce110_ipp.h"
-
-
-bool dce120_ipp_construct(
-	struct dce110_ipp *ipp,
-	struct dc_context *ctx,
-	enum controller_id id,
-	const struct dce110_ipp_reg_offsets *offset);
-
-/* CURSOR RELATED */
-void dce120_ipp_cursor_set_position(
-	struct input_pixel_processor *ipp,
-	const struct dc_cursor_position *position,
-	const struct dc_cursor_mi_param *param);
-
-void dce120_ipp_cursor_set_attributes(
-	struct input_pixel_processor *ipp,
-	const struct dc_cursor_attributes *attributes);
-
-/* DEGAMMA RELATED */
-bool dce120_ipp_set_degamma(
-	struct input_pixel_processor *ipp,
-	enum ipp_degamma_mode mode);
-
-void dce120_ipp_program_prescale(
-	struct input_pixel_processor *ipp,
-	struct ipp_prescale_params *params);
-
-void dce120_ipp_program_input_lut(
-	struct input_pixel_processor *ipp,
-	const struct dc_gamma *gamma);
-
-#endif /*__DC_IPP_DCE120_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
deleted file mode 100644
index dc81d320f6e5..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/logger_interface.h"
-
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
-
-#include "../dce110/dce110_ipp.h"
-
-
-#define DCP_REG_UPDATE_N(reg_name, n, ...)	\
-		generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__)
-
-#define DCP_REG_SET_N(reg_name, n, ...)	\
-		generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__)
-
-#define DCP_REG_UPDATE(reg, field, val)	\
-		DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-
-#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2)	\
-		DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3)	\
-		DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-#define DCP_REG_SET(reg, field, val)	\
-		DCP_REG_SET_N(reg, 1, FD(reg##__##field), val)
-
-#define DCP_REG_SET_2(reg, field1, val1, field2, val2)	\
-		DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3)	\
-		DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-/* TODO: DAL3 does not implement cursor memory control
- * MCIF_MEM_CONTROL, DMIF_CURSOR_MEM_CONTROL
- */
-static void lock(
-	struct dce110_ipp *ipp110, bool lock)
-{
-	DCP_REG_UPDATE(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, lock);
-}
-
-static bool program_control(
-	struct dce110_ipp *ipp110,
-	enum dc_cursor_color_format color_format,
-	bool enable_magnification,
-	bool inverse_transparent_clamping)
-{
-	uint32_t mode = 0;
-
-	switch (color_format) {
-	case CURSOR_MODE_MONO:
-		mode = 0;
-		break;
-	case CURSOR_MODE_COLOR_1BIT_AND:
-		mode = 1;
-		break;
-	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
-		mode = 2;
-		break;
-	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
-		mode = 3;
-		break;
-	default:
-		return false;
-	}
-
-	DCP_REG_UPDATE_3(
-		DCP0_CUR_CONTROL,
-		CURSOR_MODE, mode,
-		CURSOR_2X_MAGNIFY, enable_magnification,
-		CUR_INV_TRANS_CLAMP, inverse_transparent_clamping);
-
-	if (color_format == CURSOR_MODE_MONO) {
-		DCP_REG_SET_3(
-			DCP0_CUR_COLOR1,
-			CUR_COLOR1_BLUE, 0,
-			CUR_COLOR1_GREEN, 0,
-			CUR_COLOR1_RED, 0);
-
-		DCP_REG_SET_3(
-			DCP0_CUR_COLOR2,
-			CUR_COLOR2_BLUE, 0xff,
-			CUR_COLOR2_GREEN, 0xff,
-			CUR_COLOR2_RED, 0xff);
-	}
-	return true;
-}
-
-static void program_address(
-	struct dce110_ipp *ipp110,
-	PHYSICAL_ADDRESS_LOC address)
-{
-	/* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor
-	 * surface base address in byte. It is 4K byte aligned.
-	 * The correct way to program cursor surface address is to first write
-	 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS
-	 */
-
-	DCP_REG_SET(
-		DCP0_CUR_SURFACE_ADDRESS_HIGH,
-		CURSOR_SURFACE_ADDRESS_HIGH, address.high_part);
-
-	DCP_REG_SET(
-		DCP0_CUR_SURFACE_ADDRESS,
-		CURSOR_SURFACE_ADDRESS, address.low_part);
-}
-
-void dce120_ipp_cursor_set_position(
-	struct input_pixel_processor *ipp,
-	const struct dc_cursor_position *position,
-	const struct dc_cursor_mi_param *param)
-{
-	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-
-	/* lock cursor registers */
-	lock(ipp110, true);
-
-	/* Flag passed in structure differentiates cursor enable/disable. */
-	/* Update if it differs from cached state. */
-	DCP_REG_UPDATE(DCP0_CUR_CONTROL, CURSOR_EN, position->enable);
-
-	DCP_REG_SET_2(
-		DCP0_CUR_POSITION,
-		CURSOR_X_POSITION, position->x,
-		CURSOR_Y_POSITION, position->y);
-
-	DCP_REG_SET_2(
-		DCP0_CUR_HOT_SPOT,
-		CURSOR_HOT_SPOT_X, position->x_hotspot,
-		CURSOR_HOT_SPOT_Y, position->y_hotspot);
-
-	/* unlock cursor registers */
-	lock(ipp110, false);
-}
-
-void dce120_ipp_cursor_set_attributes(
-	struct input_pixel_processor *ipp,
-	const struct dc_cursor_attributes *attributes)
-{
-	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-	/* Lock cursor registers */
-	lock(ipp110, true);
-
-	/* Program cursor control */
-	program_control(
-		ipp110,
-		attributes->color_format,
-		attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
-		attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
-
-	/*
-	 * Program cursor size -- NOTE: HW spec specifies that HW register
-	 * stores size as (height - 1, width - 1)
-	 */
-	DCP_REG_SET_2(
-		DCP0_CUR_SIZE,
-		CURSOR_WIDTH, attributes->width-1,
-		CURSOR_HEIGHT, attributes->height-1);
-
-	/* Program cursor surface address */
-	program_address(ipp110, attributes->address);
-
-	/* Unlock Cursor registers. */
-	lock(ipp110, false);
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
deleted file mode 100644
index 7aa5a49c01e2..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/logger_interface.h"
-#include "include/fixed31_32.h"
-#include "basics/conversion.h"
-
-#include "vega10/DC/dce_12_0_offset.h"
-#include "vega10/DC/dce_12_0_sh_mask.h"
-#include "vega10/soc15ip.h"
-
-#include "../dce110/dce110_ipp.h"
-
-#define DCP_REG_UPDATE_N(reg_name, n, ...)	\
-		generic_reg_update_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__)
-
-#define DCP_REG_SET_N(reg_name, n, ...)	\
-		generic_reg_set_soc15(ipp110->base.ctx, ipp110->offsets.dcp_offset, reg_name, n, __VA_ARGS__)
-
-#define DCP_REG_UPDATE(reg, field, val)	\
-		DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-
-#define DCP_REG_UPDATE_2(reg, field1, val1, field2, val2)	\
-		DCP_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DCP_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3)	\
-		DCP_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-#define DCP_REG_SET(reg, field, val)	\
-		DCP_REG_SET_N(reg, 1, FD(reg##__##field), val)
-
-#define DCP_REG_SET_2(reg, field1, val1, field2, val2)	\
-		DCP_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-
-#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3)	\
-		DCP_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-
-
-bool dce120_ipp_set_degamma(
-	struct input_pixel_processor *ipp,
-	enum ipp_degamma_mode mode)
-{
-	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
-
-	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||
-			mode == IPP_DEGAMMA_MODE_HW_sRGB);
-
-	DCP_REG_SET_3(
-		DCP0_DEGAMMA_CONTROL,
-		GRPH_DEGAMMA_MODE, degamma_type,
-		CURSOR_DEGAMMA_MODE, degamma_type,
-		CURSOR2_DEGAMMA_MODE, degamma_type);
-
-	return true;
-}
-
-void dce120_ipp_program_prescale(
-	struct input_pixel_processor *ipp,
-	struct ipp_prescale_params *params)
-{
-	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-
-	/* set to bypass mode first before change */
-	DCP_REG_UPDATE(
-		DCP0_PRESCALE_GRPH_CONTROL,
-		GRPH_PRESCALE_BYPASS,
-		1);
-
-	DCP_REG_SET_2(
-		DCP0_PRESCALE_VALUES_GRPH_R,
-		GRPH_PRESCALE_SCALE_R, params->scale,
-		GRPH_PRESCALE_BIAS_R, params->bias);
-
-	DCP_REG_SET_2(
-		DCP0_PRESCALE_VALUES_GRPH_G,
-		GRPH_PRESCALE_SCALE_G, params->scale,
-		GRPH_PRESCALE_BIAS_G, params->bias);
-
-	DCP_REG_SET_2(
-		DCP0_PRESCALE_VALUES_GRPH_B,
-		GRPH_PRESCALE_SCALE_B, params->scale,
-		GRPH_PRESCALE_BIAS_B, params->bias);
-
-	if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
-		DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL,
-			       GRPH_PRESCALE_BYPASS, 0);
-
-		/* If prescale is in use, then legacy lut should be bypassed */
-		DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL,
-			       GRPH_INPUT_GAMMA_MODE, 1);
-	}
-}
-
-static void dce120_helper_select_lut(struct dce110_ipp *ipp110)
-{
-	/* enable all */
-	DCP_REG_SET(
-		DCP0_DC_LUT_WRITE_EN_MASK,
-		DC_LUT_WRITE_EN_MASK,
-		0x7);
-
-	/* 256 entry mode */
-	DCP_REG_UPDATE(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
-
-	/* LUT-256, unsigned, integer, new u0.12 format */
-	DCP_REG_SET_3(
-		DCP0_DC_LUT_CONTROL,
-		DC_LUT_DATA_R_FORMAT, 3,
-		DC_LUT_DATA_G_FORMAT, 3,
-		DC_LUT_DATA_B_FORMAT, 3);
-
-	/* start from index 0 */
-	DCP_REG_SET(
-		DCP0_DC_LUT_RW_INDEX,
-		DC_LUT_RW_INDEX,
-		0);
-}
-
-void dce120_ipp_program_input_lut(
-	struct input_pixel_processor *ipp,
-	const struct dc_gamma *gamma)
-{
-	int i;
-	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-
-	/* power on LUT memory */
-	DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1);
-
-	dce120_helper_select_lut(ipp110);
-
-	for (i = 0; i < INPUT_LUT_ENTRIES; i++) {
-		DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]);
-		DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]);
-		DCP_REG_SET(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]);
-	}
-
-	/* power off LUT memory */
-	DCP_REG_SET(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0);
-
-	/* bypass prescale, enable legacy LUT */
-	DCP_REG_UPDATE(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
-	DCP_REG_UPDATE(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index f677a77ca6e0..207d07b29e81 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -40,7 +40,7 @@
 #include "dce/dce_opp.h"
 #include "dce/dce_clock_source.h"
 #include "dce/dce_clocks.h"
-#include "dce120_ipp.h"
+#include "dce/dce_ipp.h"
 #include "dce110/dce110_mem_input.h"
 #include "dce120/dce120_mem_input.h"
 
@@ -174,6 +174,28 @@ static const struct dce_abm_mask abm_mask = {
 		ABM_MASK_SH_LIST_DCE110(_MASK)
 };
 
+#define ipp_regs(id)\
+[id] = {\
+		IPP_COMMON_REG_LIST_DCE_BASE(id)\
+}
+
+static const struct dce_ipp_registers ipp_regs[] = {
+		ipp_regs(0),
+		ipp_regs(1),
+		ipp_regs(2),
+		ipp_regs(3),
+		ipp_regs(4),
+		ipp_regs(5)
+};
+
+static const struct dce_ipp_shift ipp_shift = {
+		IPP_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
+};
+
+static const struct dce_ipp_mask ipp_mask = {
+		IPP_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
+};
+
 #define transform_regs(id)\
 [id] = {\
 		XFM_COMMON_REG_LIST_DCE110(id)\
@@ -354,27 +376,6 @@ struct output_pixel_processor *dce120_opp_create(
 	return NULL;
 }
 
-static const struct dce110_ipp_reg_offsets dce120_ipp_reg_offsets[] = {
-	{
-		.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-	},
-	{
-		.dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-	},
-	{
-		.dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-	},
-	{
-		.dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-	},
-	{
-		.dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-	},
-	{
-		.dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-	}
-};
-
 static const struct dce110_mem_input_reg_offsets dce120_mi_reg_offsets[] = {
 	{
 		.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
@@ -498,7 +499,7 @@ static struct timing_generator *dce120_timing_generator_create(
 
 static void dce120_ipp_destroy(struct input_pixel_processor **ipp)
 {
-	dm_free(TO_DCE110_IPP(*ipp));
+	dm_free(TO_DCE_IPP(*ipp));
 	*ipp = NULL;
 }
 
@@ -622,21 +623,18 @@ struct link_encoder *dce120_link_encoder_create(
 }
 
 static struct input_pixel_processor *dce120_ipp_create(
-	struct dc_context *ctx,
-	uint32_t inst,
-	const struct dce110_ipp_reg_offsets *offset)
+	struct dc_context *ctx, uint32_t inst)
 {
-	struct dce110_ipp *ipp = dm_alloc(sizeof(struct dce110_ipp));
+	struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
 
-	if (!ipp)
+	if (!ipp) {
+		BREAK_TO_DEBUGGER();
 		return NULL;
+	}
 
-	if (dce120_ipp_construct(ipp, ctx, inst, offset))
-		return &ipp->base;
-
-	BREAK_TO_DEBUGGER();
-	dm_free(ipp);
-	return NULL;
+	dce_ipp_construct(ipp, ctx, inst,
+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
+	return &ipp->base;
 }
 
 static struct stream_encoder *dce120_stream_encoder_create(
@@ -1025,8 +1023,7 @@ static bool construct(
 			goto controller_create_fail;
 		}
 
-		pool->base.ipps[i] = dce120_ipp_create(ctx, i,
-				&dce120_ipp_reg_offsets[i]);
+		pool->base.ipps[i] = dce120_ipp_create(ctx, i);
 		if (pool->base.ipps[i] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(