diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2018-05-23 23:21:54 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-07-06 00:38:28 +0300 |
| commit | fab55d61b9f04693abc6fdbc92e3fdf3872915b1 (patch) | |
| tree | 627d4d45df338118de051c49f0e7d81c1db9024d /drivers/gpu/drm/amd/display/dc/dce100 | |
| parent | 765b26836430e9d9ebef95fced42dd167b4ccad6 (diff) | |
| download | linux-fab55d61b9f04693abc6fdbc92e3fdf3872915b1.tar.xz | |
drm/amd/display: redesign dce/dcn clock voltage update request
The goal of this change is to move clock programming and voltage
requests to a single function. As of this change only dce is affected.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce100')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 49 |
1 files changed, 43 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index 41f83ecd7469..aabf7ca9b241 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -125,17 +125,54 @@ static void dce100_pplib_apply_display_requirements( dc->prev_display_config = *pp_display_cfg; } +/* unit: in_khz before mode set, get pixel clock from context. ASIC register + * may not be programmed yet + */ +static uint32_t get_max_pixel_clock_for_all_paths( + struct dc *dc, + struct dc_state *context) +{ + uint32_t max_pix_clk = 0; + int i; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) + continue; + + /* do not check under lay */ + if (pipe_ctx->top_pipe) + continue; + + if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk) + max_pix_clk = + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; + } + + if (max_pix_clk == 0) + ASSERT(0); + + return max_pix_clk; +} + void dce100_set_bandwidth( struct dc *dc, struct dc_state *context, bool decrease_allowed) { - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { - dc->res_pool->display_clock->funcs->set_clock( - dc->res_pool->display_clock, - context->bw.dce.dispclk_khz * 115 / 100); - dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; - } + struct dc_clocks req_clks; + + req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; + req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context); + + dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); + + dc->res_pool->display_clock->funcs->update_clocks( + dc->res_pool->display_clock, + &req_clks, + decrease_allowed); + dce100_pplib_apply_display_requirements(dc, context); } |