diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2020-08-19 02:24:03 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-26 23:40:18 +0300 |
| commit | f8646661f713fb7d33ebe404d418bd3fa55c383e (patch) | |
| tree | 473f046a55f7336acdf0950ae8956bb8424d8441 /drivers/gpu/drm/amd/amdgpu | |
| parent | b04e48bcac08ae900b5ea77a86f90356f51cf26c (diff) | |
| download | linux-f8646661f713fb7d33ebe404d418bd3fa55c383e.tar.xz | |
drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it. It's also DCN, not DCE, so remove it from the
DCE12 header.
No functional change.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e1a0ae327cf5..a858912eb094 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -67,6 +67,9 @@ #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 + static const u32 golden_settings_vega10_hdp[] = { @@ -1282,7 +1285,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) static void gmc_v9_0_restore_registers(struct amdgpu_device *adev) { if (adev->asic_type == CHIP_RAVEN) - WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); + WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); } /** @@ -1394,7 +1397,7 @@ static int gmc_v9_0_hw_init(void *handle) static void gmc_v9_0_save_registers(struct amdgpu_device *adev) { if (adev->asic_type == CHIP_RAVEN) - adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); + adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); } /** |