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authorPiotr Redlewski <predlewski@gmail.com>2017-11-10 21:28:01 +0300
committerAlex Deucher <alexander.deucher@amd.com>2017-12-06 20:47:22 +0300
commitc1fe75c9e42c8c598a7fb810ecc4f7be258e700c (patch)
tree3193f160fa5826c52f23f64181dfd00c5925c7ec /drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
parentfa2123dbccdc881fae02aaf8b05758db53d62955 (diff)
downloadlinux-c1fe75c9e42c8c598a7fb810ecc4f7be258e700c.tar.xz
drm/amd/amdgpu: fix UVD mc offsets
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Piotr Redlewski <predlewski@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 0c01825a8b9e..0e8b887cf03e 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -603,7 +603,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
upper_32_bits(adev->uvd.gpu_addr));
offset = AMDGPU_UVD_FIRMWARE_OFFSET;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+ size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
WREG32(mmUVD_VCPU_CACHE_SIZE0, size);