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| author | Andrey Grodzovsky <andrey.grodzovsky@amd.com> | 2019-07-26 21:07:42 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 19:00:44 +0300 |
| commit | c43b849f890af2b638b3bea79a4203875bcc54d7 (patch) | |
| tree | 3dd5a6962f78c8ea83208600ee41b786fa63dfba /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | e97204ead61c79c292761c5c934a02dfe9967b71 (diff) | |
| download | linux-c43b849f890af2b638b3bea79a4203875bcc54d7.tar.xz | |
drm/amdgpu: Use new mode2 reset interface for RV.
Integrate the mode2 reset into rest sequence.
v2:
Check ppfuncs pointer for NULL
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 2ccca8aafcaa..90a51490c6a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -509,6 +509,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev) return 0; } +static int soc15_mode2_reset(struct amdgpu_device *adev) +{ + if (!adev->powerplay.pp_funcs || + !adev->powerplay.pp_funcs->asic_reset_mode_2) + return -ENOENT; + + return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); +} + static enum amd_reset_method soc15_asic_reset_method(struct amdgpu_device *adev) { @@ -547,14 +556,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev) static int soc15_asic_reset(struct amdgpu_device *adev) { - int ret; - - if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) - ret = soc15_asic_baco_reset(adev); - else - ret = soc15_asic_mode1_reset(adev); - - return ret; + switch (soc15_asic_reset_method(adev)) { + case AMD_RESET_METHOD_BACO: + return soc15_asic_baco_reset(adev); + case AMD_RESET_METHOD_MODE2: + return soc15_mode2_reset(adev); + default: + return soc15_asic_mode1_reset(adev); + } } /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, |