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| author | Jiange Zhao <Jiange.Zhao@amd.com> | 2020-11-25 16:56:05 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-12-15 19:35:35 +0300 |
| commit | 3aa883ac8eea38281f97a7409d2922e6f343bf6c (patch) | |
| tree | c0e49686259c2200413fc3750f899324320b7a02 /drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | |
| parent | 325f4b59f6361df0e20a39acd3b89c265d6ca2a8 (diff) | |
| download | linux-3aa883ac8eea38281f97a7409d2922e6f343bf6c.tar.xz | |
drm/amdgpu/SRIOV: Extend VF reset request wait period
In Virtualization case, when one VF is sending too many
FLR requests, hypervisor would stop responding to this
VF's request for a long period of time. This is called
event guard. During this period of cooling time, guest
driver should wait instead of doing other things. After
this period of time, guest driver would resume reset
process and return to normal.
Currently, guest driver would wait 12 seconds and return fail
if it doesn't get response from host.
Solution: extend this waiting time in guest driver and poll
response periodically. Poll happens every 6 seconds and it will
last for 60 seconds.
v2: change the max repetition times from number to macro.
Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index 666ed99cc14b..dd5c1e6ce009 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -200,7 +200,16 @@ static int xgpu_nv_send_access_requests(struct amdgpu_device *adev, static int xgpu_nv_request_reset(struct amdgpu_device *adev) { - return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); + int ret, i = 0; + + while (i < NV_MAILBOX_POLL_MSG_REP_MAX) { + ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); + if (!ret) + break; + i++; + } + + return ret; } static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev, |