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authorEric Huang <jinhuieric.huang@amd.com>2021-02-28 00:51:19 +0300
committerAlex Deucher <alexander.deucher@amd.com>2021-03-24 06:00:44 +0300
commit06bfc045d54cd7cb769aab5af45f6022c2ce77a7 (patch)
tree2c5fc9d9ef32273f75fe9b72982767a3478f66ed /drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
parent761d86d37f86ebba77e59fa59ccef4dc2f38674f (diff)
downloadlinux-06bfc045d54cd7cb769aab5af45f6022c2ce77a7.tar.xz
drm/amdgpu: set CPU mapping of vram as cached for A+A mode
New A+A HW supports cached vram mapped to cpu. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0ea1b68e7bb9..c5fea144b759 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -673,7 +673,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
mem->bus.offset += adev->gmc.aper_base;
mem->bus.is_iomem = true;
- mem->bus.caching = ttm_write_combined;
+ if (adev->gmc.xgmi.connected_to_cpu)
+ mem->bus.caching = ttm_cached;
+ else
+ mem->bus.caching = ttm_write_combined;
break;
default:
return -EINVAL;