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authorMonk Liu <Monk.Liu@amd.com>2017-05-01 13:09:22 +0300
committerAlex Deucher <alexander.deucher@amd.com>2017-05-25 00:40:26 +0300
commit3b4d68e993d941ec993660f10bacdfd556731dc7 (patch)
tree9ade8a92d523488e5b3833200e21113843f7dd0b /drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
parentd951eeddface8bcdcb4fd95066801abface55c21 (diff)
downloadlinux-3b4d68e993d941ec993660f10bacdfd556731dc7.tar.xz
drm/amdgpu:use FRAME_CNTL for new GFX ucode (v2)
AI affected: CP/HW team requires KMD insert FRAME_CONTROL(end) after the last IB and before the fence of this DMAframe. this is to make sure the cache are flushed, and it's a must change no matter MCBP/SR-IOV or bare-metal case because new CP hw won't do the cache flush for each IB anymore, it just leaves it to KMD now. with this patch, certain MCBP hang issue when rendering vulkan/chained-ib are resolved. v2: drop gfx8 changes. gfx8 is not affected (Alex) Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 944443c5b90a..2b7b3c56d446 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -142,6 +142,7 @@ struct amdgpu_ring_funcs {
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+ void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
};
struct amdgpu_ring {