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authorSamuel Holland <samuel@sholland.org>2019-12-29 05:59:21 +0300
committerMaxime Ripard <maxime@cerno.tech>2020-01-02 12:27:56 +0300
commit675a6d467b432c8b4a0703ded02e6ef068e0c7e9 (patch)
tree744bb3275daba154491cbf04afa43d44fddc1d0b /drivers/clk
parent47d64fef1f3ffbdf960d3330b9865fc9f12fdf84 (diff)
downloadlinux-675a6d467b432c8b4a0703ded02e6ef068e0c7e9.tar.xz
clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition
Like the APB0 clock on previous chips, this is a simple single-parent clock with an M divider. Use the equivalent helper macro instead of writing out the whole clock description manually. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c12
1 files changed, 1 insertions, 11 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 45a1ed3fe674..df9c01831699 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -51,17 +51,7 @@ static struct ccu_div ar100_clk = {
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
-static struct ccu_div r_apb1_clk = {
- .div = _SUNXI_CCU_DIV(0, 2),
-
- .common = {
- .reg = 0x00c,
- .hw.init = CLK_HW_INIT("r-apb1",
- "r-ahb",
- &ccu_div_ops,
- 0),
- },
-};
+static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
static struct ccu_div r_apb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),