diff options
| author | Rongyi Chen <chenyi@tt-cool.com> | 2018-08-10 18:16:38 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2018-08-27 05:35:04 +0300 |
| commit | 58c0f79887d5e425fe6a9fd542778e50df69e9c6 (patch) | |
| tree | 6de7e85a2f62c31958b4f130647a5d84fc230200 /drivers/clk/sunxi-ng | |
| parent | 2852bfbf4f168fec27049ad9ed20941fc9e84b95 (diff) | |
| download | linux-58c0f79887d5e425fe6a9fd542778e50df69e9c6.tar.xz | |
clk: sunxi-ng: h6: fix PWM gate/reset offset
Currently the register offset of the PWM bus gate in Allwinner H6 clock
driver is wrong.
Fix this issue.
Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Rongyi Chen <chenyi@tt-cool.com>
[Icenowy: refactor commit message]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk/sunxi-ng')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 0f7a0ffd3f70..d425b47cef17 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -352,7 +352,7 @@ static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 0x79c, BIT(0), 0); -static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x79c, BIT(0), 0); +static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); |