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| author | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-03-11 18:25:35 +0300 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2021-03-23 19:03:35 +0300 |
| commit | a01be32fccbb8cc0f6a3a155cf6bb5f528a4e20c (patch) | |
| tree | f6c2ed27e1a13dca0e2d635ec6051efdc6cf3512 /drivers/clk/socfpga | |
| parent | 3409fb0987dc0e3199c13e4de6ad678cdbeae007 (diff) | |
| download | linux-a01be32fccbb8cc0f6a3a155cf6bb5f528a4e20c.tar.xz | |
clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers
On a multiplatform kernel there is little benefit in splitting each
clock driver per platform because space savings are minimal. Such split
also complicates the code, especially after adding compile testing.
Build all arm64 Intel SoCFPGA clocks together with one entry in
Makefile. This also removed duplicated line in the Makefile (selecting
common part of clocks per platform).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga')
| -rw-r--r-- | drivers/clk/socfpga/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/clk/socfpga/Makefile | 7 |
2 files changed, 6 insertions, 7 deletions
diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index 3c30617169bf..bc102e0f0be0 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 config CLK_INTEL_SOCFPGA64 bool - # Intel Agilex / N5X clock controller support - default (ARCH_AGILEX || ARCH_N5X) - depends on ARCH_AGILEX || ARCH_N5X + # Intel Stratix / Agilex / N5X clock controller support + default (ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10) + depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index c6db8dd4ab35..ebd3538d12de 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-agilex.o -obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \ + clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ + clk-agilex.o |