diff options
| author | Ilia Lin <ilialin@codeaurora.org> | 2020-07-03 11:49:43 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-07-11 03:09:20 +0300 |
| commit | 2283f9e03328b2437abddf446027931631af1031 (patch) | |
| tree | f0a758d25ecc78c3b24d3387f3ec0810caf539be /drivers/clk/qcom | |
| parent | 6d0efeb14bbe2350a94ba07b403a686d731c5179 (diff) | |
| download | linux-2283f9e03328b2437abddf446027931631af1031.tar.xz | |
dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLY
The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.
The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1593766185-16346-4-git-send-email-loic.poulain@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom')
0 files changed, 0 insertions, 0 deletions