diff options
| author | Ingo Molnar <mingo@kernel.org> | 2019-02-11 10:01:50 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2019-02-11 10:01:50 +0300 |
| commit | c9ba7560c550fe6c1f4a8f0666bea41d2a349d1d (patch) | |
| tree | b15d53e69f73b160b4625e91187cd436c5a3e683 /drivers/clk/qcom/gcc-sdm845.c | |
| parent | f6783319737f28e4436a69611853a5a098cbe974 (diff) | |
| parent | d13937116f1e82bf508a6325111b322c30c85eb9 (diff) | |
| download | linux-c9ba7560c550fe6c1f4a8f0666bea41d2a349d1d.tar.xz | |
Merge tag 'v5.0-rc6' into sched/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/gcc-sdm845.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-sdm845.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index c782e62dd98b..58fa5c247af1 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -115,8 +115,8 @@ static const char * const gcc_parent_names_6[] = { "core_bi_pll_test_se", }; -static const char * const gcc_parent_names_7[] = { - "bi_tcxo", +static const char * const gcc_parent_names_7_ao[] = { + "bi_tcxo_ao", "gpll0", "gpll0_out_even", "core_bi_pll_test_se", @@ -128,6 +128,12 @@ static const char * const gcc_parent_names_8[] = { "core_bi_pll_test_se", }; +static const char * const gcc_parent_names_8_ao[] = { + "bi_tcxo_ao", + "gpll0", + "core_bi_pll_test_se", +}; + static const struct parent_map gcc_parent_map_10[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, @@ -210,7 +216,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk_src", - .parent_names = gcc_parent_names_7, + .parent_names = gcc_parent_names_7_ao, .num_parents = 4, .ops = &clk_rcg2_ops, }, @@ -229,7 +235,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_rbcpr_clk_src", - .parent_names = gcc_parent_names_8, + .parent_names = gcc_parent_names_8_ao, .num_parents = 3, .ops = &clk_rcg2_ops, }, |