diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 18:55:29 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 11:49:23 +0300 |
| commit | 6b71aceceb09918daf37a40a1221077599040be3 (patch) | |
| tree | c0976c81450a6b568ac7b18e3442ccea7b6d7cc6 /drivers/clk/meson | |
| parent | 07f45e2ecc1ba1ce75d80768caf2267256cd135d (diff) | |
| download | linux-6b71aceceb09918daf37a40a1221077599040be3.tar.xz | |
clk: meson: axg: add the fractional part of the fixed_pll
The fixed_pll also has a fractional part. On axg s400 board, without
this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll
being the root of the peripheral clock tree, this error is propagated to
the rest of the clocks
Adding the definition of the parameter fixes the problem
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/axg.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 8e37bbf305e9..a1ac0ff67e5f 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -37,6 +37,11 @@ static struct meson_clk_pll axg_fixed_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_MPLL_CNTL2, + .shift = 0, + .width = 12, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "fixed_pll", |