diff options
| author | Yixun Lan <yixun.lan@amlogic.com> | 2018-07-03 00:31:18 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-07-09 14:49:11 +0300 |
| commit | cddcb20b2bb36401e038d0ae41ba8a956d91f82e (patch) | |
| tree | e2fcecaea7ea56f7dd808008f7066fd06307ae16 /drivers/clk/meson/axg.h | |
| parent | 85ddc1a32cace10bc8b7dc5dfae98b6a1785fc0c (diff) | |
| download | linux-cddcb20b2bb36401e038d0ae41ba8a956d91f82e.tar.xz | |
clk: meson-axg: add clocks required by pcie driver
Adding clocks for the pcie driver. Due to the ASIC design,
the pcie controller re-use part of the mipi clock logic,
so the mipi clock is also added.
Tested-by: Jianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[amended to remove unnecessary locales]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.h')
| -rw-r--r-- | drivers/clk/meson/axg.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index b421df6a7ea0..6e55ebd6c77d 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -16,6 +16,7 @@ * Register offsets from the data sheet must be multiplied by 4 before * adding them to the base address to get the right value. */ +#define HHI_MIPI_CNTL0 0x00 #define HHI_GP0_PLL_CNTL 0x40 #define HHI_GP0_PLL_CNTL2 0x44 #define HHI_GP0_PLL_CNTL3 0x48 @@ -127,8 +128,11 @@ #define CLKID_FCLK_DIV4_DIV 73 #define CLKID_FCLK_DIV5_DIV 74 #define CLKID_FCLK_DIV7_DIV 75 +#define CLKID_PCIE_PLL 76 +#define CLKID_PCIE_MUX 77 +#define CLKID_PCIE_REF 78 -#define NR_CLKS 76 +#define NR_CLKS 82 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> |