diff options
| author | Viresh Kumar <viresh.kumar@linaro.org> | 2018-07-20 13:11:50 +0300 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2018-07-22 00:29:11 +0300 |
| commit | 945d004788319fb5863de3b2e4831064902dd10c (patch) | |
| tree | b45a745e6d2c83b7b3005dd2b3f692793003a1ce /arch | |
| parent | 4d4ef9c422904b3057cd443999decd17b5b3e398 (diff) | |
| download | linux-945d004788319fb5863de3b2e4831064902dd10c.tar.xz | |
ARM: dts: berlin: Add missing OPP properties for CPUs
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing properties (clocks, clock latency) as well to
make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/berlin2.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/berlin2q.dtsi | 33 |
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index db67377af266..d2f7d984bba5 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -50,6 +50,16 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; }; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 516a7ce25791..99d6872a6dfc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -45,6 +45,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; cpu2: cpu@2 { @@ -52,6 +63,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <2>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; cpu3: cpu@3 { @@ -59,6 +81,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <3>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; }; |