diff options
| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2010-11-19 10:23:52 +0300 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-11-24 09:34:04 +0300 |
| commit | 421b446abeec55bed1251fab80cb5c12be58b773 (patch) | |
| tree | 7c9b92368cf986b776f9ecf457683761a592a941 /arch | |
| parent | b16a2892b9852839307894cc429b7a7b145138a7 (diff) | |
| download | linux-421b446abeec55bed1251fab80cb5c12be58b773.tar.xz | |
ARM: mach-shmobile: clock-sh7372: remove bogus pllc2 clock toggling.
The PLLC2 clock was utilizing the same sort of enable/disable without
regard to usecount approach that the FSIDIV clock was when being used as
a PLL pass-through. This forces the enable/disable through the clock
framework, which now prevents the clock from being ripped out or modified
underneath users that have an existing handle on it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-shmobile/board-ap4evb.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 12 |
2 files changed, 7 insertions, 10 deletions
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index e084b423146e..d440e5f456ad 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -969,6 +969,11 @@ static int __init hdmi_init_pm_clock(void) goto out; } + ret = clk_enable(&sh7372_pllc2_clk); + if (ret < 0) { + pr_err("Cannot enable pllc2 clock\n"); + goto out; + } pr_debug("PLLC2 set frequency %lu\n", rate); ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index cbeca2849918..e18a1241a95e 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -230,21 +230,13 @@ static int pllc2_set_rate(struct clk *clk, if (idx < 0) return idx; - if (rate == clk->parent->rate) { - pllc2_disable(clk); - return 0; - } + if (rate == clk->parent->rate) + return -EINVAL; value = __raw_readl(PLLC2CR) & ~(0x3f << 24); - if (value & 0x80000000) - pllc2_disable(clk); - __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR); - if (value & 0x80000000) - return pllc2_enable(clk); - return 0; } |