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| author | Yan, Zheng <zheng.z.yan@intel.com> | 2013-07-18 13:02:23 +0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2013-09-02 10:42:47 +0400 |
| commit | 53ad0447208d3f5897f673ca0b16c776583eedba (patch) | |
| tree | 6966be991efc98edce985854defe71b62ff4f116 /arch/x86/kernel/vsyscall_64.c | |
| parent | ea79ca0de05198159bcb8a45479122a75e4a5861 (diff) | |
| download | linux-53ad0447208d3f5897f673ca0b16c776583eedba.tar.xz | |
perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code
for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event.
Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1374138144-17278-1-git-send-email-zheng.z.yan@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/vsyscall_64.c')
0 files changed, 0 insertions, 0 deletions