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authorJoel Stanley <joel@jms.id.au>2019-07-04 04:43:37 +0300
committerJoel Stanley <joel@jms.id.au>2019-07-04 04:43:41 +0300
commit2caf12c9ed84a39b383d0f237d1506b7e9a95bdf (patch)
tree8ba503d4cb7079f73d4b71f306c3e0c120cec53b /arch/x86/kernel/cpu/bugs.c
parentd83aec28b086ee676056638d77ac93b06ec3d4b1 (diff)
parent8584aaf1c3262ca17d1e4a614ede9179ef462bb0 (diff)
downloadlinux-dev-5.1.tar.xz
Merge tag 'v5.1.16' into dev-5.1dev-5.1
This is the 5.1.16 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/x86/kernel/cpu/bugs.c')
-rw-r--r--arch/x86/kernel/cpu/bugs.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 03b4cc0ec3a7..66ca906aa790 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -836,6 +836,16 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
}
/*
+ * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
+ * bit in the mask to allow guests to use the mitigation even in the
+ * case where the host does not enable it.
+ */
+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+ static_cpu_has(X86_FEATURE_AMD_SSBD)) {
+ x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
+ }
+
+ /*
* We have three CPU feature flags that are in play here:
* - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
* - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
@@ -852,7 +862,6 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
x86_amd_ssb_disable();
} else {
x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
- x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
}
}