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| author | Al Viro <viro@zeniv.linux.org.uk> | 2008-08-18 03:13:17 +0400 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2008-10-23 09:55:19 +0400 |
| commit | 8ede0bdb63305d3353efd97e9af6210afb05734e (patch) | |
| tree | a9500a323d0a2dcadca43c23b5c20186f6d9b724 /arch/um/include/asm/cache.h | |
| parent | 8569c9140bd41089f9b6be8837ca421102714a90 (diff) | |
| download | linux-8ede0bdb63305d3353efd97e9af6210afb05734e.tar.xz | |
x86, um: initial part of asm-um move
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/um/include/asm/cache.h')
| -rw-r--r-- | arch/um/include/asm/cache.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/um/include/asm/cache.h b/arch/um/include/asm/cache.h new file mode 100644 index 000000000000..19e1bdd67416 --- /dev/null +++ b/arch/um/include/asm/cache.h @@ -0,0 +1,17 @@ +#ifndef __UM_CACHE_H +#define __UM_CACHE_H + + +#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) +# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) +#elif defined(CONFIG_UML_X86) /* 64-bit */ +# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ +#else +/* XXX: this was taken from x86, now it's completely random. Luckily only + * affects SMP padding. */ +# define L1_CACHE_SHIFT 5 +#endif + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#endif |