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authorPaul Mundt <lethal@linux-sh.org>2008-07-29 17:46:55 +0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-29 17:46:55 +0400
commit93dc544cf4892b9188d7d0d4946b0394020b4551 (patch)
tree5b518ad829e53e23304cc463e8013b66f1c087a0 /arch/sh/include/cpu-sh2a/cpu/watchdog.h
parent1795cf48b322b4d19230a40dbe7181acedd34a94 (diff)
downloadlinux-93dc544cf4892b9188d7d0d4946b0394020b4551.tar.xz
sh: Provide common CPU headers, prune the SH-2 and SH-2A directories.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh2a/cpu/watchdog.h')
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/watchdog.h70
1 files changed, 1 insertions, 69 deletions
diff --git a/arch/sh/include/cpu-sh2a/cpu/watchdog.h b/arch/sh/include/cpu-sh2a/cpu/watchdog.h
index 393161c9c6d0..e7e8259e468c 100644
--- a/arch/sh/include/cpu-sh2a/cpu/watchdog.h
+++ b/arch/sh/include/cpu-sh2a/cpu/watchdog.h
@@ -1,69 +1 @@
-/*
- * include/asm-sh/cpu-sh2/watchdog.h
- *
- * Copyright (C) 2002, 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH2_WATCHDOG_H
-#define __ASM_CPU_SH2_WATCHDOG_H
-
-/*
- * More SH-2 brilliance .. its not good enough that we can't read
- * and write the same sizes to WTCNT, now we have to read and write
- * with different sizes at different addresses for WTCNT _and_ RSTCSR.
- *
- * At least on the bright side no one has managed to screw over WTCSR
- * in this fashion .. yet.
- */
-/* Register definitions */
-#define WTCNT 0xfffffe80
-#define WTCSR 0xfffffe80
-#define RSTCSR 0xfffffe82
-
-#define WTCNT_R (WTCNT + 1)
-#define RSTCSR_R (RSTCSR + 1)
-
-/* Bit definitions */
-#define WTCSR_IOVF 0x80
-#define WTCSR_WT 0x40
-#define WTCSR_TME 0x20
-#define WTCSR_RSTS 0x00
-
-#define RSTCSR_RSTS 0x20
-
-/**
- * sh_wdt_read_rstcsr - Read from Reset Control/Status Register
- *
- * Reads back the RSTCSR value.
- */
-static inline __u8 sh_wdt_read_rstcsr(void)
-{
- /*
- * Same read/write brain-damage as for WTCNT here..
- */
- return ctrl_inb(RSTCSR_R);
-}
-
-/**
- * sh_wdt_write_csr - Write to Reset Control/Status Register
- *
- * @val: Value to write
- *
- * Writes the given value @val to the lower byte of the control/status
- * register. The upper byte is set manually on each write.
- */
-static inline void sh_wdt_write_rstcsr(__u8 val)
-{
- /*
- * Note: Due to the brain-damaged nature of this register,
- * we can't presently touch the WOVF bit, since the upper byte
- * has to be swapped for this. So just leave it alone..
- */
- ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
-}
-
-#endif /* __ASM_CPU_SH2_WATCHDOG_H */
-
+#include <cpu-sh2/cpu/watchdog.h>