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| author | Andrea Parri <parri.andrea@gmail.com> | 2018-02-27 05:24:11 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-04-03 05:59:43 +0300 |
| commit | 8d235b174af5d0af35ff206c15041fc2b02a0993 (patch) | |
| tree | a5fff32b1bde8022d3b6a6d4ff91a80cd4424f55 /arch/riscv | |
| parent | 0adb32858b0bddf4ada5f364a84ed60b196dbcda (diff) | |
| download | linux-8d235b174af5d0af35ff206c15041fc2b02a0993.tar.xz | |
riscv/barrier: Define __smp_{store_release,load_acquire}
Introduce __smp_{store_release,load_acquire}, and rely on the generic
definitions for smp_{store_release,load_acquire}. This avoids the use
of full ("rw,rw") fences on SMP.
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/barrier.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 5510366d169a..d4628e4b3a5e 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -38,6 +38,21 @@ #define __smp_rmb() RISCV_FENCE(r,r) #define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ +} while (0) + +#define __smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = READ_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(r,rw); \ + ___p1; \ +}) + /* * This is a very specific barrier: it's currently only used in two places in * the kernel, both in the scheduler. See include/linux/spinlock.h for the two |