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| author | Joel Stanley <joel@jms.id.au> | 2020-08-04 10:58:32 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2020-08-04 10:58:36 +0300 |
| commit | 9524588381df213554a10d3661a9200a4b7f6db2 (patch) | |
| tree | a4d281b99dcd28b9a1d3077299c26a5671abff88 /arch/riscv/include/asm | |
| parent | 666e403461fd046b37bc95bba49e82ca6a758bea (diff) | |
| parent | 67da9e2c2b730b9b788ace749d22d769cf11ee2b (diff) | |
| download | linux-dev-5.7.tar.xz | |
Merge tag 'v5.7.12' into dev-5.7dev-5.7
This is the 5.7.12 stable release
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/riscv/include/asm')
| -rw-r--r-- | arch/riscv/include/asm/barrier.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 3f1737f301cc..d0e24aaa2aa0 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -58,8 +58,16 @@ do { \ * The AQ/RL pair provides a RCpc critical section, but there's not really any * way we can take advantage of that here because the ordering is only enforced * on that one lock. Thus, we're just doing a full fence. + * + * Since we allow writeX to be called from preemptive regions we need at least + * an "o" in the predecessor set to ensure device writes are visible before the + * task is marked as available for scheduling on a new hart. While I don't see + * any concrete reason we need a full IO fence, it seems safer to just upgrade + * this in order to avoid any IO crossing a scheduling boundary. In both + * instances the scheduler pairs this with an mb(), so nothing is necessary on + * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) #include <asm-generic/barrier.h> |