diff options
| author | Paul Mackerras <paulus@ozlabs.org> | 2017-08-30 07:12:28 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-09-01 09:39:49 +0300 |
| commit | d120cdbce68c3739f94f733bec376460fb9cbc14 (patch) | |
| tree | d0c8d39cdf6352660a9fe35fc1c1cbfbfbea78e6 /arch/powerpc/include/asm | |
| parent | 350779a29f11f80ac66a8b38a7718ad30f003f18 (diff) | |
| download | linux-d120cdbce68c3739f94f733bec376460fb9cbc14.tar.xz | |
powerpc/64: Fix update forms of loads and stores to write 64-bit EA
When a 64-bit processor is executing in 32-bit mode, the update forms
of load and store instructions are required by the architecture to
write the full 64-bit effective address into the RA register, though
only the bottom 32 bits are used to address memory. Currently,
the instruction emulation code writes the truncated address to the
RA register. This fixes it by keeping the full 64-bit EA in the
instruction_op structure, truncating the address in emulate_step()
where it is used to address memory, rather than in the address
computations in analyse_instr().
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/sstep.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h index 980197024c0b..4fcc2c9a6ed5 100644 --- a/arch/powerpc/include/asm/sstep.h +++ b/arch/powerpc/include/asm/sstep.h @@ -25,7 +25,7 @@ struct pt_regs; enum instruction_type { COMPUTE, /* arith/logical/CR op, etc. */ - LOAD, + LOAD, /* load and store types need to be contiguous */ LOAD_MULTI, LOAD_FP, LOAD_VMX, @@ -52,6 +52,8 @@ enum instruction_type { #define INSTR_TYPE_MASK 0x1f +#define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX) + /* Compute flags, ORed in with type */ #define SETREG 0x20 #define SETCC 0x40 |