diff options
| author | John Crispin <john@phrozen.org> | 2016-12-20 21:12:41 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-01-03 18:34:47 +0300 |
| commit | 2517caf19dbfac3b39f2db5500c5fd03c4370e81 (patch) | |
| tree | ab3c132c1c7fae3dc4f6e686acf891058896a27d /arch/mips/ralink/mt7620.c | |
| parent | 4f79ddec04229c966326d90cc3cfd414401dea22 (diff) | |
| download | linux-2517caf19dbfac3b39f2db5500c5fd03c4370e81.tar.xz | |
MIPS: ralink: Add missing I2C and I2S clocks.
This patch adds two additional clocks required by the audio interface of
the SoCs.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14897/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink/mt7620.c')
| -rw-r--r-- | arch/mips/ralink/mt7620.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 3c7c9bf57bf3..6f0fdfd1e32a 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -509,6 +509,7 @@ void __init ralink_clk_init(void) unsigned long sys_rate; unsigned long dram_rate; unsigned long periph_rate; + unsigned long pcmi2s_rate; xtal_rate = mt7620_get_xtal_rate(); @@ -523,6 +524,7 @@ void __init ralink_clk_init(void) cpu_rate = MHZ(575); dram_rate = sys_rate = cpu_rate / 3; periph_rate = MHZ(40); + pcmi2s_rate = MHZ(480); ralink_clk_add("10000d00.uartlite", periph_rate); ralink_clk_add("10000e00.uartlite", periph_rate); @@ -534,6 +536,7 @@ void __init ralink_clk_init(void) dram_rate = mt7620_get_dram_rate(pll_rate); sys_rate = mt7620_get_sys_rate(cpu_rate); periph_rate = mt7620_get_periph_rate(xtal_rate); + pcmi2s_rate = periph_rate; pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), RINT(xtal_rate), RFRAC(xtal_rate), @@ -555,6 +558,8 @@ void __init ralink_clk_init(void) ralink_clk_add("cpu", cpu_rate); ralink_clk_add("10000100.timer", periph_rate); ralink_clk_add("10000120.watchdog", periph_rate); + ralink_clk_add("10000900.i2c", periph_rate); + ralink_clk_add("10000a00.i2s", pcmi2s_rate); ralink_clk_add("10000b00.spi", sys_rate); ralink_clk_add("10000b40.spi", sys_rate); ralink_clk_add("10000c00.uartlite", periph_rate); |