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| author | John Crispin <blogic@openwrt.org> | 2011-03-30 11:27:48 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 12:55:41 +0400 |
| commit | 8ec6d93508f705dacafd5fcd058c69ef405002f9 (patch) | |
| tree | b26de8b55fdae858ac2d1b48b563f0315a6c683a /arch/mips/lantiq/Makefile | |
| parent | 171bb2f19ed6f3627f4f783f658f2f475b2fbd50 (diff) | |
| download | linux-8ec6d93508f705dacafd5fcd058c69ef405002f9.tar.xz | |
MIPS: Lantiq: add SoC specific code for XWAY family
Add support for the Lantiq XWAY family of Mips24KEc SoCs.
* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)
The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.
The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function
int lq_gpio_request(unsigned int pin, unsigned int alt0,
unsigned int alt1, unsigned int dir, const char *name);
which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.
The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lantiq/Makefile')
| -rw-r--r-- | arch/mips/lantiq/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile index 6a30de671f23..a268391eb45e 100644 --- a/arch/mips/lantiq/Makefile +++ b/arch/mips/lantiq/Makefile @@ -7,3 +7,5 @@ obj-y := irq.o setup.o clk.o prom.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ |