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authorJoshua Kinard <kumba@gentoo.org>2020-05-18 02:24:39 +0300
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-05-24 10:28:49 +0300
commitb34a1a712024cd1cf50e405102eb9f71961fd6cd (patch)
tree70534a30a7a230f0a25c574ccac047eaa715197b /arch/mips/include/asm/mach-ip30
parentec7a93188a75b57b9f704db6862e7137f01aa80b (diff)
downloadlinux-b34a1a712024cd1cf50e405102eb9f71961fd6cd.tar.xz
MIPS: SGI-IP30: Reorder the macros in war.h
Fix the ordering of the macros in arch/mips/mach-ip30/war.h to match those in arch/mips/mach-ip27/war.h. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ip30')
-rw-r--r--arch/mips/include/asm/mach-ip30/war.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index ad3352d3d203..a1fa0c1f5300 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -8,18 +8,17 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
-
#ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1
#else
#define R10000_LLSC_WAR 0
#endif
+#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */