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authorDavid Daney <david.daney@cavium.com>2013-05-23 00:46:44 +0400
committerRalf Baechle <ralf@linux-mips.org>2013-06-10 20:01:25 +0400
commit0ec315121c8391a14bbeb5eecc146c470dfc00cb (patch)
tree4450a34838c9066a1fa6e31303e9919305c14b90 /arch/mips/include/asm/mach-cavium-octeon
parent02a49d5144c58a2b9826946934533a7a9f28c2ec (diff)
downloadlinux-0ec315121c8391a14bbeb5eecc146c470dfc00cb.tar.xz
MIPS: OCTEON: Get rid of CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
When you turn it off, the kernel is unusable, so get rid of the option and always allow unaligned access. The Octeon specific memcpy intentionally does unaligned accesses and it must not fault. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5303/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon')
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1e7dbb192657..1668ee57acb9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -34,15 +34,10 @@
ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
-#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
# Disable unaligned load/store support but leave HW fixup enabled
+ # Needed for octeon specific memcpy
or v0, v0, 0x5001
xor v0, v0, 0x1001
-#else
- # Disable unaligned load/store and HW fixup support
- or v0, v0, 0x5001
- xor v0, v0, 0x5001
-#endif
# Read the processor ID register
mfc0 v1, CP0_PRID_REG
# Disable instruction prefetching (Octeon Pass1 errata)