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| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-01-06 14:09:24 +0300 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 18:37:22 +0300 |
| commit | 0038df2240ff01c666e5b55120ef9c3f15c281a4 (patch) | |
| tree | 6e243ae11c00a0f0ed31572a8f0f30ba03851308 /arch/mips/include/asm/atomic.h | |
| parent | fa998ebbc02d11aa33a621e6f41cb15ce87e6b9e (diff) | |
| download | linux-0038df2240ff01c666e5b55120ef9c3f15c281a4.tar.xz | |
MIPS: asm: atomic: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to
set the correct ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/atomic.h')
| -rw-r--r-- | arch/mips/include/asm/atomic.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 3a44c2f17e53..26d436336f2e 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -61,7 +61,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \ \ do { \ __asm__ __volatile__( \ - " .set arch=r4000 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " ll %0, %1 # atomic_" #op "\n" \ " " #asm_op " %0, %2 \n" \ " sc %0, %1 \n" \ @@ -104,7 +104,7 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \ \ do { \ __asm__ __volatile__( \ - " .set arch=r4000 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " ll %1, %2 # atomic_" #op "_return \n" \ " " #asm_op " %0, %1, %3 \n" \ " sc %0, %2 \n" \ @@ -178,7 +178,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) int temp; __asm__ __volatile__( - " .set arch=r4000 \n" + " .set "MIPS_ISA_LEVEL" \n" "1: ll %1, %2 # atomic_sub_if_positive\n" " subu %0, %1, %3 \n" " bltz %0, 1f \n" @@ -340,7 +340,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \ \ do { \ __asm__ __volatile__( \ - " .set arch=r4000 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " lld %0, %1 # atomic64_" #op "\n" \ " " #asm_op " %0, %2 \n" \ " scd %0, %1 \n" \ @@ -383,7 +383,7 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \ \ do { \ __asm__ __volatile__( \ - " .set arch=r4000 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " lld %1, %2 # atomic64_" #op "_return\n" \ " " #asm_op " %0, %1, %3 \n" \ " scd %0, %2 \n" \ @@ -459,7 +459,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) long temp; __asm__ __volatile__( - " .set arch=r4000 \n" + " .set "MIPS_ISA_LEVEL" \n" "1: lld %1, %2 # atomic64_sub_if_positive\n" " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" |