summaryrefslogtreecommitdiff
path: root/arch/mips/boot/dts/ralink/mt7620a.dtsi
diff options
context:
space:
mode:
authorAndrew Bresticker <abrestic@chromium.org>2014-12-25 20:48:57 +0300
committerRalf Baechle <ralf@linux-mips.org>2015-04-01 18:21:34 +0300
commit8c0b9ee8665c43ee370108930ff51cab9a545c1c (patch)
treeaa6bd64b02f384db1e2a1cfbdd1ad08388980a71 /arch/mips/boot/dts/ralink/mt7620a.dtsi
parentec9ddad3c6a5789373e4f67009a0dea276febc47 (diff)
downloadlinux-8c0b9ee8665c43ee370108930ff51cab9a545c1c.tar.xz
MIPS: Move device-trees into vendor sub-directories
Move the MIPS device-trees into the appropriate vendor sub-directories. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8835/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/boot/dts/ralink/mt7620a.dtsi')
-rw-r--r--arch/mips/boot/dts/ralink/mt7620a.dtsi58
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
new file mode 100644
index 000000000000..08bf24fefe9f
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -0,0 +1,58 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mtk7620a-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ };
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "ralink,mt7620a-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ intc: intc@200 {
+ compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ memc@300 {
+ compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uartlite@c00 {
+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
+ reg = <0xc00 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+
+ reg-shift = <2>;
+ };
+ };
+};