diff options
| author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-31 08:57:05 +0400 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-31 08:57:05 +0400 |
| commit | 5bc65793cbf8da0d35f19ef025dda22887e79e80 (patch) | |
| tree | 8291998abd73055de6f487fafa174ee2a5d3afee /arch/arm | |
| parent | 6edae708bf77e012d855a7e2c7766f211d234f4f (diff) | |
| parent | 3f0a6766e0cc5a577805732e5adb50a585c58175 (diff) | |
| download | linux-5bc65793cbf8da0d35f19ef025dda22887e79e80.tar.xz | |
[SCSI] Merge up to linux-2.6 head
Conflicts:
drivers/scsi/jazz_esp.c
Same changes made by both SCSI and SPARC trees: problem with UTF-8
conversion in the copyright.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'arch/arm')
102 files changed, 409 insertions, 482 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e55bbd32dcac..50d9f3e4e0f1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -287,6 +287,7 @@ config ARCH_IXP2000 config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS help diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 6fbe7722aa44..b36b1e8a105d 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -6,7 +6,7 @@ * copy data to/from buffers located outside the DMA region. This * only works for systems in which DMA memory is at the bottom of * RAM, the remainder of memory is at the top and the DMA memory - * can be marked as ZONE_DMA. Anything beyond that such as discontigous + * can be marked as ZONE_DMA. Anything beyond that such as discontiguous * DMA windows will require custom implementations that reserve memory * areas at early bootup. * diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4deece5fbdf4..0c89bd35e06f 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq) * unmask it, in the same way we need to unmask an interrupt when * we first enable it. * - * The GIC has a seperate notion of "end of interrupt" to re-enable + * The GIC has a separate notion of "end of interrupt" to re-enable * an interrupt after handling, in order to support hardware * prioritisation. * @@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) } #endif -static void fastcall gic_handle_cascade_irq(unsigned int irq, - struct irq_desc *desc) +static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = get_irq_data(irq); struct irq_chip *chip = get_irq_chip(irq); - unsigned int cascade_irq; + unsigned int cascade_irq, gic_irq; unsigned long status; /* primary controller ack'ing */ @@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq, status = readl(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); - cascade_irq = (status & 0x3ff); - if (cascade_irq > 1020) + gic_irq = (status & 0x3ff); + if (gic_irq == 1023) goto out; - if (cascade_irq < 32 || cascade_irq >= NR_IRQS) { - do_bad_IRQ(cascade_irq, desc); - goto out; - } - cascade_irq += chip_data->irq_offset; - generic_handle_irq(cascade_irq); + cascade_irq = gic_irq + chip_data->irq_offset; + if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) + do_bad_IRQ(cascade_irq, desc); + else + generic_handle_irq(cascade_irq); out: /* primary controller unmasking */ diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c index c94864c5b1af..aad4d94ba8f5 100644 --- a/arch/arm/common/sharpsl_param.c +++ b/arch/arm/common/sharpsl_param.c @@ -20,7 +20,7 @@ * typically including LCD parameters are loaded by the bootloader at the * address PARAM_BASE. As the kernel will overwrite them, we need to store * them early in the boot process, then pass them to the appropriate drivers. - * Not all devices use all paramaters but the format is common to all. + * Not all devices use all parameters but the format is common to all. */ #ifdef CONFIG_ARCH_SA1100 #define PARAM_BASE 0xe8ffc000 diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 5972df2b9af4..3bf3a927ae22 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -153,7 +153,7 @@ static void sharpsl_battery_thread(struct work_struct *private_) sharpsl_pm.battstat.mainbat_percent = percent; } - dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %d\n", voltage, + dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage, sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); /* If battery is low. limit backlight intensity to save power. */ @@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data) } /* Charging Finished Interrupt (Not present on Corgi) */ -/* Can trigger at the same time as an AC staus change so +/* Can trigger at the same time as an AC status change so delay until after that has been processed */ irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id) { @@ -625,7 +625,7 @@ static int sharpsl_fatal_check(void) } temp = get_select_val(buff); - dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %d\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); + dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) || (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt))) @@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void) static int sharpsl_off_charge_error(void) { - dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n"); + dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n"); sharpsl_pm.machinfo->charge(0); sharpsl_pm_led(SHARPSL_LED_ERROR); sharpsl_pm.charge_mode = CHRG_ERROR; @@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void) time = RCNR; while(1) { - /* Check if any wakeup event had occured */ + /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; /* Check for timeout */ if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) return 1; if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) { - dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n"); + dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n"); sharpsl_pm.full_count++; sharpsl_pm.machinfo->charge(0); mdelay(SHARPSL_CHARGE_WAIT_TIME); @@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void) time = RCNR; while(1) { - /* Check if any wakeup event had occured */ + /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; /* Check for timeout */ @@ -774,6 +774,8 @@ static struct pm_ops sharpsl_pm_ops = { static int __init sharpsl_pm_probe(struct platform_device *pdev) { + int ret; + if (!pdev->dev.platform_data) return -EINVAL; @@ -792,8 +794,10 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) sharpsl_pm.machinfo->init(); - device_create_file(&pdev->dev, &dev_attr_battery_percentage); - device_create_file(&pdev->dev, &dev_attr_battery_voltage); + ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage); + ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage); + if (ret != 0) + dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret); apm_get_power_status = sharpsl_apm_get_power_status; diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 9179e8220314..f73d62e8ab60 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -57,7 +57,7 @@ extern void fp_enter(void); #define EXPORT_SYMBOL_ALIAS(sym,orig) \ EXPORT_CRC_ALIAS(sym) \ static const struct kernel_symbol __ksymtab_##sym \ - __attribute_used__ __attribute__((section("__ksymtab"))) = \ + __used __attribute__((section("__ksymtab"))) = \ { (unsigned long)&orig, #sym }; /* diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 3c078e346753..3278e713c32a 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -85,7 +85,7 @@ int main(void) DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); -#if __LINUX_ARM_ARCH__ >= 6 +#ifdef CONFIG_CPU_HAS_ASID DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); BLANK(); #endif diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index ae89cdd82b16..19326d7cdeb3 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -357,6 +357,10 @@ /* 345 */ CALL(sys_getcpu) CALL(sys_ni_syscall) /* eventually epoll_pwait */ CALL(sys_kexec_load) + CALL(sys_utimensat) + CALL(sys_signalfd) +/* 350 */ CALL(sys_timerfd) + CALL(sys_eventfd) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 0453dcc757b4..650eac1bc0a6 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -918,7 +918,7 @@ static int c_show(struct seq_file *m, void *v) if ((processor_id & 0x0008f000) == 0x00000000) { /* pre-ARM7 */ - seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4); + seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4); } else { if ((processor_id & 0x0008f000) == 0x00007000) { /* ARM7 */ diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index 8b63ad89d0a8..ae31deb2d065 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -13,7 +13,7 @@ int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high, /* * Check current frame pointer is within bounds */ - if ((fp - 12) < low || fp + 4 >= high) + if (fp < (low + 12) || fp + 4 >= high) break; frame = (struct stackframe *)(fp - 12); diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 3d4fcbc16276..1ca2d5174fcb 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) EXPORT_SYMBOL(kernel_execve); /* - * Since loff_t is a 64 bit type we avoid a lot of ABI hastle + * Since loff_t is a 64 bit type we avoid a lot of ABI hassle * with a different argument ordering. */ asmlinkage long sys_arm_fadvise64_64(int fd, int advice, diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index e4156e7868ce..2b7a8f5d8cf2 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -90,7 +90,7 @@ SECTIONS __exception_text_start = .; *(.exception.text) __exception_text_end = .; - *(.text) + TEXT_TEXT SCHED_TEXT LOCK_TEXT #ifdef CONFIG_MMU @@ -158,7 +158,7 @@ SECTIONS /* * and the usual data section */ - *(.data) + DATA_DATA CONSTRUCTORS _edata = .; diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index 542251021744..2e787d40d599 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -47,7 +47,7 @@ * @store: store instruction * * Note: we can trivially conditionalise the store instruction - * to avoid dirting the data cache. + * to avoid dirtying the data cache. */ .macro testop, instr, store add r1, r1, r0, lsr #3 diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index b4518619063a..76ec856cd4f9 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = { .pullup_pin = AT91_PIN_PD9, }; -/* FIXME: user dependend */ +/* FIXME: user dependant */ // static struct at91_cf_data __initdata carmeva_cf_data = { // .det_pin = AT91_PIN_PB0, // .rst_pin = AT91_PIN_PC5, @@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = { .chip_select = 0, .max_speed_hz = 10 * 1000 * 1000, }, - { /* User accessable spi - cs1 (250KHz) */ + { /* User accessible spi - cs1 (250KHz) */ .modalias = "spi-cs1", .chip_select = 1, .max_speed_hz = 250 * 1000, }, - { /* User accessable spi - cs2 (1MHz) */ + { /* User accessible spi - cs2 (1MHz) */ .modalias = "spi-cs2", .chip_select = 2, .max_speed_hz = 1 * 1000 * 1000, }, - { /* User accessable spi - cs3 (10MHz) */ + { /* User accessible spi - cs3 (10MHz) */ .modalias = "spi-cs3", .chip_select = 3, .max_speed_hz = 10 * 1000 * 1000, diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c index 6043c38c0a9e..af497896a96c 100644 --- a/arch/arm/mach-at91/board-dk.c +++ b/arch/arm/mach-at91/board-dk.c @@ -132,7 +132,7 @@ static struct mtd_partition __initdata dk_nand_partition[] = { }, }; -static struct mtd_partition *nand_partitions(int size, int *num_partitions) +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) { *num_partitions = ARRAY_SIZE(dk_nand_partition); return dk_nand_partition; diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index 76f6e1e553ea..7d9b1a278fd6 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -96,7 +96,7 @@ static struct mtd_partition __initdata kb9202_nand_partition[] = { }, }; -static struct mtd_partition *nand_partitions(int size, int *num_partitions) +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) { *num_partitions = ARRAY_SIZE(kb9202_nand_partition); return kb9202_nand_partition; diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 1f0c8a400b3a..26ca8ab3f62a 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -178,7 +178,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { }, }; -static struct mtd_partition *nand_partitions(int size, int *num_partitions) +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) { *num_partitions = ARRAY_SIZE(ek_nand_partition); return ek_nand_partition; diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index f57458559fb6..c164c8e58ae6 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -180,7 +180,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { }, }; -static struct mtd_partition *nand_partitions(int size, int *num_partitions) +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) { *num_partitions = ARRAY_SIZE(ek_nand_partition); return ek_nand_partition; diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index 30c79aca84d4..9b61320f295a 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -87,7 +87,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { }, }; -static struct mtd_partition *nand_partitions(int size, int *num_partitions) +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) { *num_partitions = ARRAY_SIZE(ek_nand_partition); return ek_nand_partition; diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c index 4f984fde7375..35eb232a649a 100644 --- a/arch/arm/mach-footbridge/cats-pci.c +++ b/arch/arm/mach-footbridge/cats-pci.c @@ -45,7 +45,7 @@ static struct hw_pci cats_pci __initdata = { .postinit = dc21285_postinit, }; -static int cats_pci_init(void) +static int __init cats_pci_init(void) { if (machine_is_cats()) pci_common_init(&cats_pci); diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index 82e420d6fd19..0a1a25fb8ba8 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id) } /* - * mask multiplexed timer irq's + * mask multiplexed timer IRQs */ static void inline mask_timerx_irq (u32 irq) { @@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq) } /* - * unmask multiplexed timer irq's + * unmask multiplexed timer IRQs */ static void inline unmask_timerx_irq (u32 irq) { diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c index 7e70e0b0b989..467d899fbe75 100644 --- a/arch/arm/mach-imx/cpufreq.c +++ b/arch/arm/mach-imx/cpufreq.c @@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy, if(mpctl0) { CSCR |= CSCR_MPLL_RESTART; - /* Wait until MPLL is stablized */ + /* Wait until MPLL is stabilized */ while( CSCR & CSCR_MPLL_RESTART ); imx_set_async_mode(); diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c index 6d50d85a618c..bc6fb02d213b 100644 --- a/arch/arm/mach-imx/dma.c +++ b/arch/arm/mach-imx/dma.c @@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch, * The function setups DMA channel source and destination addresses for transfer * specified by provided parameters. The scatter-gather emulation is disabled, * because linear data block - * form the physical address range is transfered. + * form the physical address range is transferred. * Return value: if incorrect parameters are provided -%EINVAL. * Zero indicates success. */ @@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory * or %DMA_MODE_WRITE from memory to the device * - * The function setups DMA channel state and registers to be ready for transfer + * The function sets up DMA channel state and registers to be ready for transfer * specified by provided parameters. The scatter-gather emulation is set up * according to the parameters. * @@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, * * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x * - * Be carefull there and do not mistakenly mix source and target device + * Be careful here and do not mistakenly mix source and target device * port sizes constants, they are really different: * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 @@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) /* * The cleaning of @sg field would be questionable * there, because its value can help to compute - * remaining/transfered bytes count in the handler + * remaining/transferred bytes count in the handler */ /*imx_dma_channels[i].sg = NULL;*/ diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c index 7a7fa51ec62c..1c474cf709ca 100644 --- a/arch/arm/mach-imx/generic.c +++ b/arch/arm/mach-imx/generic.c @@ -201,7 +201,6 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info) { imx_mmc_device.dev.platform_data = info; } -EXPORT_SYMBOL(imx_set_mmc_info); static struct imxfb_mach_info imx_fb_info; diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index ebb255bdce8a..158daaf9e3b0 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -12,4 +12,3 @@ obj-$(CONFIG_LEDS) += leds.o obj-$(CONFIG_PCI) += pci_v3.o pci.o obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 897c21c2fb5b..e9c82deb791d 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -257,23 +257,7 @@ integrator_timer_interrupt(int irq, void *dev_id) */ writel(1, TIMER1_VA_BASE + TIMER_INTCLR); - /* - * the clock tick routines are only processed on the - * primary CPU - */ - if (hard_smp_processor_id() == 0) { - timer_tick(); -#ifdef CONFIG_SMP - smp_send_timer(); -#endif - } - -#ifdef CONFIG_SMP - /* - * this is the ARM equivalent of the APIC timer interrupt - */ - update_process_times(user_mode(get_irq_regs())); -#endif /* CONFIG_SMP */ + timer_tick(); write_sequnlock(&xtime_lock); diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S deleted file mode 100644 index ceaa88e30d70..000000000000 --- a/arch/arm/mach-integrator/headsmp.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> - - __INIT - -/* - * Integrator specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(integrator_secondary_startup) - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - ldr r6, [r6, r4] -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - -1: .long . - .long phys_pen_release diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index af9ebccac7c1..d4d8134ce567 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -33,6 +33,7 @@ #include <asm/irq.h> #include <asm/system.h> #include <asm/mach/pci.h> +#include <asm/irq_regs.h> #include <asm/hardware/pci_v3.h> diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c deleted file mode 100644 index 613b841a10f3..000000000000 --- a/arch/arm/mach-integrator/platsmp.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * linux/arch/arm/mach-cintegrator/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/errno.h> -#include <linux/mm.h> - -#include <asm/atomic.h> -#include <asm/cacheflush.h> -#include <asm/delay.h> -#include <asm/mmu_context.h> -#include <asm/ptrace.h> -#include <asm/smp.h> - -extern void integrator_secondary_startup(void); - -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int __cpuinitdata pen_release = -1; -unsigned long __cpuinitdata phys_pen_release = 0; - -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * the primary core may have used a "cross call" soft interrupt - * to get this processor out of WFI in the BootMonitor - make - * sure that we are no longer being sent this soft interrupt - */ - smp_cross_call_done(cpumask_of_cpu(cpu)); - - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - secondary_scan_irqs(); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - pen_release = -1; - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - pen_release = cpu; - flush_cache_all(); - - /* - * XXX - * - * This is a later addition to the booting protocol: the - * bootMonitor now puts secondary cores into WFI, so - * poke_milo() no longer gets the cores moving; we need - * to send a soft interrupt to wake the secondary core. - * Use smp_cross_call() for this, since there's little - * point duplicating the code here - */ - smp_cross_call(cpumask_of_cpu(cpu)); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -static void __init poke_milo(void) -{ - extern void secondary_startup(void); - - /* nobody is to be released from the pen yet */ - pen_release = -1; - - phys_pen_release = virt_to_phys(&pen_release); - - /* - * write the address of secondary startup into the system-wide - * flags register, then clear the bottom two bits, which is what - * BootMonitor is waiting for - */ -#if 1 -#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30 - __raw_writel(virt_to_phys(integrator_secondary_startup), - (IO_ADDRESS(INTEGRATOR_HDR_BASE) + - CINTEGRATOR_HDR_FLAGSS_OFFSET)); -#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34 - __raw_writel(3, - (IO_ADDRESS(INTEGRATOR_HDR_BASE) + - CINTEGRATOR_HDR_FLAGSC_OFFSET)); -#endif - - mb(); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -void __init smp_init_cpus(void) -{ - unsigned int i, ncores = get_core_count(); - - for (i = 0; i < ncores; i++) - cpu_set(i, cpu_possible_map); -} - -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - unsigned int ncores = get_core_count(); - unsigned int cpu = smp_processor_id(); - int i; - - /* sanity check */ - if (ncores == 0) { - printk(KERN_ERR - "Integrator/CP: strange CM count of 0? Default to 1\n"); - - ncores = 1; - } - - if (ncores > NR_CPUS) { - printk(KERN_WARNING - "Integrator/CP: no. of cores (%d) greater than configured " - "maximum of %d - clipping\n", - ncores, NR_CPUS); - ncores = NR_CPUS; - } - - /* - * start with some more config for the Boot CPU, now that - * the world is a bit more alive (which was not the case - * when smp_prepare_boot_cpu() was called) - */ - smp_store_cpu_info(cpu); - - /* - * are we trying to boot more cores than exist? - */ - if (max_cpus > ncores) - max_cpus = ncores; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - cpu_set(i, cpu_present_map); - - /* - * Do we need any more CPUs? If so, then let them know where - * to start. Note that, on modern versions of MILO, the "poke" - * doesn't actually do anything until each individual core is - * sent a soft interrupt to get it out of WFI - */ - if (max_cpus > 1) - poke_milo(); -} diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index 5791addd436b..69f07b25b3c9 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -30,77 +30,65 @@ /* INTCTL0 CP6 R0 Page 4 */ -static inline u32 read_intctl_0(void) +static u32 read_intctl_0(void) { u32 val; asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_0(u32 val) +static void write_intctl_0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); } /* INTCTL1 CP6 R1 Page 4 */ -static inline u32 read_intctl_1(void) +static u32 read_intctl_1(void) { u32 val; asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_1(u32 val) +static void write_intctl_1(u32 val) { asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); } /* INTCTL2 CP6 R2 Page 4 */ -static inline u32 read_intctl_2(void) +static u32 read_intctl_2(void) { u32 val; asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_2(u32 val) +static void write_intctl_2(u32 val) { asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); } /* INTCTL3 CP6 R3 Page 4 */ -static inline u32 read_intctl_3(void) +static u32 read_intctl_3(void) { u32 val; asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_3(u32 val) +static void write_intctl_3(u32 val) { asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); } /* INTSTR0 CP6 R0 Page 5 */ -static inline u32 read_intstr_0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val)); - return val; -} -static inline void write_intstr_0(u32 val) +static void write_intstr_0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); } /* INTSTR1 CP6 R1 Page 5 */ -static inline u32 read_intstr_1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val)); - return val; -} static void write_intstr_1(u32 val) { asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); @@ -108,12 +96,6 @@ static void write_intstr_1(u32 val) /* INTSTR2 CP6 R2 Page 5 */ -static inline u32 read_intstr_2(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val)); - return val; -} static void write_intstr_2(u32 val) { asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); @@ -121,12 +103,6 @@ static void write_intstr_2(u32 val) /* INTSTR3 CP6 R3 Page 5 */ -static inline u32 read_intstr_3(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val)); - return val; -} static void write_intstr_3(u32 val) { asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); @@ -134,12 +110,6 @@ static void write_intstr_3(u32 val) /* INTBASE CP6 R0 Page 2 */ -static inline u32 read_intbase(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val)); - return val; -} static void write_intbase(u32 val) { asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); @@ -147,12 +117,6 @@ static void write_intbase(u32 val) /* INTSIZE CP6 R2 Page 2 */ -static inline u32 read_intsize(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val)); - return val; -} static void write_intsize(u32 val) { asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index 2d2369302220..63ef1124ca5c 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); /* IMIPR0 CP6 R8 Page 1 */ -static inline u32 read_imipr_0(void) +static u32 read_imipr_0(void) { u32 val; asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_0(u32 val) +static void write_imipr_0(u32 val) { asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); } /* IMIPR1 CP6 R9 Page 1 */ -static inline u32 read_imipr_1(void) +static u32 read_imipr_1(void) { u32 val; asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_1(u32 val) +static void write_imipr_1(u32 val) { asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); } /* IMIPR2 CP6 R10 Page 1 */ -static inline u32 read_imipr_2(void) +static u32 read_imipr_2(void) { u32 val; asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_2(u32 val) +static void write_imipr_2(u32 val) { asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); } /* IMIPR3 CP6 R11 Page 1 */ -static inline u32 read_imipr_3(void) +static u32 read_imipr_3(void) { u32 val; asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_3(u32 val) +static void write_imipr_3(u32 val) { asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); } @@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) write_msi_msg(irq, &msg); set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); - return irq; + return 0; } diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 1c9e94c38b7e..9d63d7f260ca 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -19,10 +19,11 @@ #include <linux/pci.h> #include <linux/delay.h> - +#include <linux/jiffies.h> #include <asm/irq.h> #include <asm/hardware.h> #include <asm/sizes.h> +#include <asm/signal.h> #include <asm/mach/pci.h> #include <asm/arch/pci.h> @@ -144,7 +145,7 @@ void iop13xx_map_pci_memory(void) } } -static inline int iop13xx_atu_function(int atu) +static int iop13xx_atu_function(int atu) { int func = 0; /* the function number depends on the value of the @@ -259,7 +260,7 @@ static int iop13xx_atux_pci_status(int clear) * data. Note that the data dependency on %0 encourages an abort * to be detected before we return. */ -static inline u32 iop13xx_atux_read(unsigned long addr) +static u32 iop13xx_atux_read(unsigned long addr) { u32 val; @@ -387,7 +388,7 @@ static int iop13xx_atue_pci_status(int clear) return err; } -static inline int __init +static int iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) { WARN_ON(idsel != 0); @@ -401,7 +402,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } } -static inline u32 iop13xx_atue_read(unsigned long addr) +static u32 iop13xx_atue_read(unsigned long addr) { u32 val; @@ -989,7 +990,7 @@ void __init iop13xx_pci_init(void) "imprecise external abort"); } -/* intialize the pci memory space. handle any combination of +/* initialize the pci memory space. handle any combination of * atue and atux enabled/disabled */ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 45f4f13ae11b..5776fd884115 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -75,7 +75,7 @@ void __init glantank_map_io(void) #define INTC IRQ_IOP32X_XINT2 #define INTD IRQ_IOP32X_XINT3 -static inline int __init +static int __init glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[][4] = { diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 7b21c6e13e59..d4eefbea1fe6 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -104,7 +104,7 @@ void __init iq31244_map_io(void) /* * EP80219/IQ31244 PCI. */ -static inline int __init +static int __init ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; @@ -140,7 +140,7 @@ static struct hw_pci ep80219_pci __initdata = { .map_irq = ep80219_pci_map_irq, }; -static inline int __init +static int __init iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index bc25fb91e7b9..8d9f49164a84 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -72,7 +72,7 @@ void __init iq80321_map_io(void) /* * IQ80321 PCI. */ -static inline int __init +static int __init iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 82598dc18d80..c971171c2905 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -21,12 +21,12 @@ static u32 iop32x_mask; -static inline void intctl_write(u32 val) +static void intctl_write(u32 val) { asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); } -static inline void intstr_write(u32 val) +static void intstr_write(u32 val) { asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); } diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 5f07344d96f3..d55005d64781 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -76,7 +76,7 @@ void __init n2100_map_io(void) /* * N2100 PCI. */ -static inline int __init +static int __init n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 376c932830be..2b063180687a 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -55,7 +55,7 @@ static struct sys_timer iq80331_timer = { /* * IQ80331 PCI. */ -static inline int __init +static int __init iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 58c81496c6f6..7889ce3cb08e 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -55,7 +55,7 @@ static struct sys_timer iq80332_timer = { /* * IQ80332 PCI. */ -static inline int __init +static int __init iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index c65ea78a2427..f09dd054b9c0 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -22,32 +22,32 @@ static u32 iop33x_mask0; static u32 iop33x_mask1; -static inline void intctl0_write(u32 val) +static void intctl0_write(u32 val) { asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); } -static inline void intctl1_write(u32 val) +static void intctl1_write(u32 val) { asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); } -static inline void intstr0_write(u32 val) +static void intstr0_write(u32 val) { asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); } -static inline void intstr1_write(u32 val) +static void intstr1_write(u32 val) { asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); } -static inline void intbase_write(u32 val) +static void intbase_write(u32 val) { asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); } -static inline void intsize_write(u32 val) +static void intsize_write(u32 val) { asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); } diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c index 500e997ba7a4..9c49435d42c3 100644 --- a/arch/arm/mach-ixp2000/enp2611.c +++ b/arch/arm/mach-ixp2000/enp2611.c @@ -198,7 +198,7 @@ subsys_initcall(enp2611_pci_init); /************************************************************************* - * ENP-2611 Machine Intialization + * ENP-2611 Machine Initialization *************************************************************************/ static struct flash_platform_data enp2611_flash_platform_data = { .map_name = "cfi_probe", diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c index 0fdd03ab36e6..ce7c15c73004 100644 --- a/arch/arm/mach-ixp2000/ixdp2400.c +++ b/arch/arm/mach-ixp2000/ixdp2400.c @@ -164,7 +164,7 @@ int __init ixdp2400_pci_init(void) subsys_initcall(ixdp2400_pci_init); -void ixdp2400_init_irq(void) +void __init ixdp2400_init_irq(void) { ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS); } diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c index 70d247f09a7e..14f09b80ab77 100644 --- a/arch/arm/mach-ixp2000/ixdp2800.c +++ b/arch/arm/mach-ixp2000/ixdp2800.c @@ -279,7 +279,7 @@ int __init ixdp2800_pci_init(void) subsys_initcall(ixdp2800_pci_init); -void ixdp2800_init_irq(void) +void __init ixdp2800_init_irq(void) { ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS); } diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 52b368b34346..73c651e83d92 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -145,7 +145,7 @@ static struct irq_chip ixdp2x00_cpld_irq_chip = { .unmask = ixdp2x00_irq_unmask }; -void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_irqs) +void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_irqs) { unsigned int irq; @@ -195,7 +195,7 @@ void __init ixdp2x00_map_io(void) * instances of the kernel. So far so good. Peers on the PCI bus running * Linux is a common design in telecom systems. The problem is that instead * of all the devices being controlled by a single host, different - * devices are controlles by different NPUs on the same bus, leading to + * devices are controlled by different NPUs on the same bus, leading to * multiple hosts on the bus. The exact bus layout looks like: * * Bus 0 @@ -211,7 +211,7 @@ void __init ixdp2x00_map_io(void) * | | | | | * ... Dev PMC Media Eth0 Eth1 ... * - * The master controlls all but Eth1, which is controlled by the + * The master controls all but Eth1, which is controlled by the * slave. What this means is that the both the master and the slave * have to scan the bus, but only one of them can enumerate the bus. * In addition, after the bus is scanned, each kernel must remove diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 3084a5fa751c..d3d730d2fc2b 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -276,7 +276,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* Device is located after first MB bridge */ case 0x0008: if (tmp_bus == dev->bus) { - /* Device is located directy after first MB bridge */ + /* Device is located directly after first MB bridge */ switch (devpin) { case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ if (machine_is_ixdp2401()) @@ -299,7 +299,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) break; case 0x0010: if (tmp_bus == dev->bus) { - /* Device is located directy after second MB bridge */ + /* Device is located directly after second MB bridge */ /* Secondary bus of second bridge */ switch (devpin) { case DEVPIN(0, 1): /* DB#0 */ @@ -348,7 +348,7 @@ int __init ixdp2x01_pci_init(void) subsys_initcall(ixdp2x01_pci_init); /************************************************************************* - * IXDP2x01 Machine Intialization + * IXDP2x01 Machine Initialization *************************************************************************/ static struct flash_platform_data ixdp2x01_flash_platform_data = { .map_name = "cfi_probe", diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c index 5a09a90c08fb..03f4cf7f9dec 100644 --- a/arch/arm/mach-ixp2000/pci.c +++ b/arch/arm/mach-ixp2000/pci.c @@ -102,7 +102,7 @@ int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, } /* - * We don't do error checks by callling clear_master_aborts() b/c the + * We don't do error checks by calling clear_master_aborts() b/c the * assumption is that the caller did a read first to make sure a device * exists. */ diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index b644bbab7d0a..16356ffc86ae 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -389,7 +389,7 @@ struct sys_timer ixp23xx_timer = { /************************************************************************* - * IXP23xx Platform Initializaion + * IXP23xx Platform Initialization *************************************************************************/ static struct resource ixp23xx_uart_resources[] = { { diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 7a86a2516eaa..c41a6b5a0acc 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -124,7 +124,7 @@ static struct irq_chip ixdp2351_intb_chip = { .unmask = ixdp2351_intb_unmask }; -void ixdp2351_init_irq(void) +void __init ixdp2351_init_irq(void) { int irq; diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index ac7d43d23c28..227f808dc0ec 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -284,7 +284,7 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys) return 1; } -void ixp23xx_pci_slave_init(void) +void __init ixp23xx_pci_slave_init(void) { ixp23xx_pci_common_init(); } diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index d06e21b70de5..e35644961aa4 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c @@ -110,7 +110,7 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) return NO_IRQ; } -static void roadrunner_pci_preinit(void) +static void __init roadrunner_pci_preinit(void) { set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW); set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW); diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 9715ef506c24..060909870b50 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -104,9 +104,6 @@ config MACH_DSMG600 DSM-G600 RevA device. For more information on this platform, see http://www.nslu2-linux.org/wiki/DSMG600/HomePage -# -# Avila and IXDP share the same source for now. Will change in future -# config ARCH_IXDP4XX bool depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435 diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 64685da1462d..8112f726ffa0 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -283,7 +283,7 @@ static struct irqaction ixp4xx_timer_irq = { .handler = ixp4xx_timer_interrupt, }; -static void __init ixp4xx_timer_init(void) +void __init ixp4xx_timer_init(void) { /* Reset/disable counter */ *IXP4XX_OSRT1 = 0; diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 7bc94f3def1c..ad2e5b97966e 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -25,10 +25,6 @@ #include <asm/mach/pci.h> -extern void ixp4xx_pci_preinit(void); -extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); - void __init coyote_pci_preinit(void) { set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW); diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index 1caff65e22cc..1e75e105c4f7 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -18,6 +18,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> +#include <asm/mach/time.h> static struct flash_platform_data dsmg600_flash_data = { .map_name = "cfi_probe", @@ -128,6 +129,19 @@ static void dsmg600_power_off(void) gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH); } +static void __init dsmg600_timer_init(void) +{ + /* The xtal on this machine is non-standard. */ + ixp4xx_timer_freq = DSMG600_FREQ; + + /* Call standard timer_init function. */ + ixp4xx_timer_init(); +} + +static struct sys_timer dsmg600_timer = { + .init = dsmg600_timer_init, +}; + static void __init dsmg600_init(void) { ixp4xx_sys_init(); @@ -155,21 +169,13 @@ static void __init dsmg600_init(void) #endif } -static void __init dsmg600_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, struct meminfo *mi) -{ - /* The xtal on this machine is non-standard. */ - ixp4xx_timer_freq = DSMG600_FREQ; -} - MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") /* Maintainer: www.nslu2-linux.org */ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC, .boot_params = 0x00000100, - .fixup = dsmg600_fixup, .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .timer = &dsmg600_timer, .init_machine = dsmg600_init, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 30f1300e0e21..dc6725bda3c4 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-ixp4xx/gtwx5715-setup.c * - * Gemtek GTWX5715 (Linksys WRV54G) board settup + * Gemtek GTWX5715 (Linksys WRV54G) board setup * * Copyright (C) 2004 George T. Joseph * Derived from Coyote diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 509a95a692a4..d1e75b7dc3b1 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -23,10 +23,6 @@ #include <asm/mach/pci.h> -extern void ixp4xx_pci_preinit(void); -extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); - void __init ixdpg425_pci_preinit(void) { set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 9a31444d9214..78a17413ceca 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -155,7 +155,8 @@ static void __init nas100d_init(void) pm_power_off = nas100d_power_off; - /* This is only useful on a modified machine, but it is valuable + /* + * This is only useful on a modified machine, but it is valuable * to have it first in order to see debug messages, and so that * it does *not* get removed if platform_add_devices fails! */ diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index 162c266e5f8f..9bf8ccbcaccf 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -22,6 +22,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> +#include <asm/mach/time.h> static struct flash_platform_data nslu2_flash_data = { .map_name = "cfi_probe", @@ -49,26 +50,26 @@ static struct ixp4xx_i2c_pins nslu2_i2c_gpio_pins = { static struct resource nslu2_led_resources[] = { { .name = "ready", /* green led */ - .start = NSLU2_LED_GRN, - .end = NSLU2_LED_GRN, + .start = NSLU2_LED_GRN_GPIO, + .end = NSLU2_LED_GRN_GPIO, .flags = IXP4XX_GPIO_HIGH, }, { .name = "status", /* red led */ - .start = NSLU2_LED_RED, - .end = NSLU2_LED_RED, + .start = NSLU2_LED_RED_GPIO, + .end = NSLU2_LED_RED_GPIO, .flags = IXP4XX_GPIO_HIGH, }, { .name = "disk-1", - .start = NSLU2_LED_DISK1, - .end = NSLU2_LED_DISK1, + .start = NSLU2_LED_DISK1_GPIO, + .end = NSLU2_LED_DISK1_GPIO, .flags = IXP4XX_GPIO_LOW, }, { .name = "disk-2", - .start = NSLU2_LED_DISK2, - .end = NSLU2_LED_DISK2, + .start = NSLU2_LED_DISK2_GPIO, + .end = NSLU2_LED_DISK2_GPIO, .flags = IXP4XX_GPIO_LOW, }, }; @@ -157,10 +158,21 @@ static void nslu2_power_off(void) gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH); } -static void __init nslu2_init(void) +static void __init nslu2_timer_init(void) { - ixp4xx_timer_freq = NSLU2_FREQ; + /* The xtal on this machine is non-standard. */ + ixp4xx_timer_freq = NSLU2_FREQ; + + /* Call standard timer_init function. */ + ixp4xx_timer_init(); +} +static struct sys_timer nslu2_timer = { + .init = nslu2_timer_init, +}; + +static void __init nslu2_init(void) +{ ixp4xx_sys_init(); nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); @@ -169,7 +181,8 @@ static void __init nslu2_init(void) pm_power_off = nslu2_power_off; - /* This is only useful on a modified machine, but it is valuable + /* + * This is only useful on a modified machine, but it is valuable * to have it first in order to see debug messages, and so that * it does *not* get removed if platform_add_devices fails! */ @@ -185,6 +198,6 @@ MACHINE_START(NSLU2, "Linksys NSLU2") .boot_params = 0x00000100, .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .timer = &nslu2_timer, .init_machine = nslu2_init, MACHINE_END diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h index 4fb2efc4950f..df6e38ed425b 100644 --- a/arch/arm/mach-lh7a40x/lcd-panel.h +++ b/arch/arm/mach-lh7a40x/lcd-panel.h @@ -126,7 +126,7 @@ static struct clcd_panel_extra lcd_panel_extra = { */ -/* The full horozontal cycle (Th) is clock/360/400/450. */ +/* The full horizontal cycle (Th) is clock/360/400/450. */ /* The full vertical cycle (Tv) is line/251/262/280. */ #define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ @@ -162,7 +162,7 @@ static struct clcd_panel lcd_panel = { /* Logic Product Development LCD 6.4" VGA -10 */ /* Sharp PN LQ64D343 */ -/* The full horozontal cycle (Th) is clock/750/800/900. */ +/* The full horizontal cycle (Th) is clock/750/800/900. */ /* The full vertical cycle (Tv) is line/515/525/560. */ #define PIX_CLOCK_TARGET (28330000) @@ -243,7 +243,7 @@ static struct clcd_panel lcd_panel = { * (fdisk, e2fsck). And, at that speed the display may have a visible * flicker. */ -/* The full horozontal cycle (Th) is clock/832/1056/1395. */ +/* The full horizontal cycle (Th) is clock/832/1056/1395. */ #define PIX_CLOCK_TARGET (20000000) #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index dd257084441c..b97d0c54a388 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -35,7 +35,7 @@ static unsigned long ns9xxx_timer_gettimeoffset(void) { /* return the microseconds which have passed since the last interrupt * was _serviced_. That is, if an interrupt is pending or the counter - * reloads, return one periode more. */ + * reloads, return one period more. */ u32 counter1 = SYS_TR(0); int pending = SYS_ISR & (1 << IRQ_TIMER0); diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 856c681ebbbc..f6ecdd3a2478 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -38,7 +38,7 @@ config MACH_OMAP_H2 config MACH_OMAP_H3 bool "TI H3 Support" depends on ARCH_OMAP1 && ARCH_OMAP16XX - select GPIOEXPANDER_OMAP +# select GPIOEXPANDER_OMAP help TI OMAP 1710 H3 board support. Say Y here if you have such a board. diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7d0cf7af88ce..e7130293a03f 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -385,7 +385,7 @@ static void __init osk_init(void) /* Workaround for wrong CS3 (NOR flash) timing * There are some U-Boot versions out there which configure * wrong CS3 memory timings. This mainly leads to CRC - * or similiar errors if you use NOR flash (e.g. with JFFS2) + * or similar errors if you use NOR flash (e.g. with JFFS2) */ if (EMIFS_CCS(3) != EMIFS_CS3_VAL) EMIFS_CCS(3) = EMIFS_CS3_VAL; diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 4bc8a62909b9..015824185629 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -7,7 +7,7 @@ * * Original version : Laurent Gonzalez * - * Maintainters : http://palmtelinux.sf.net + * Maintainers : http://palmtelinux.sf.net * palmtelinux-developpers@lists.sf.net * * This program is free software; you can redistribute it and/or modify diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 8caee68aa090..5bb348e2e315 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -438,7 +438,7 @@ void omap_pm_suspend(void) omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); /* - * Reenable interrupts + * Re-enable interrupts */ local_irq_enable(); diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 5170481afeab..588adb5ab47f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -443,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate) /* * Check the DLL lock state, and return tue if running in unlock mode. - * This is needed to compenste for the shifted DLL value in unlock mode. + * This is needed to compensate for the shifted DLL value in unlock mode. */ static u32 omap2_dll_force_needed(void) { diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 162978fd5359..4f791866b910 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -338,7 +338,7 @@ struct prcm_config { /* * These represent optimal values for common parts, it won't work for all. * As long as you scale down, most parameters are still work, they just - * become sub-optimal. The RFR value goes in the oppisite direction. If you + * become sub-optimal. The RFR value goes in the opposite direction. If you * don't adjust it down as your clock period increases the refresh interval * will not be met. Setting all parameters for complete worst case may work, * but may cut memory performance by 2x. Due to errata the DLLs need to be @@ -384,7 +384,7 @@ struct prcm_config { * Filling in table based on H4 boards and 2430-SDPs variants available. * There are quite a few more rates combinations which could be defined. * - * When multiple values are defiend the start up will try and choose the + * When multiple values are defined the start up will try and choose the * fastest one. If a 'fast' value is defined, then automatically, the /2 * one should be included as it can be used. Generally having more that * one fast set does not make sense, as static timings need to be changed diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index a72476c24621..365b9435f748 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -40,7 +40,7 @@ #define PICTRL_ADRS 0x06 #define POLCTRL_ADRS 0x07 -/* Resgister Bit Definitions */ +/* Register Bit Definitions */ #define RESCTL_QVGA 0x01 #define RESCTL_VGA 0x00 @@ -55,11 +55,11 @@ #define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ #define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ #define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ -#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ +#define POWER0_COM_ON 0x08 /* COM Power Supply ON */ #define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ #define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ -#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ +#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */ #define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ #define PICTRL_INIT_STATE 0x01 @@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data) lcdtg_i2c_send_stop(base_data); } -/* Set Phase Adjuct */ +/* Set Phase Adjust */ static void lcdtg_set_phadadj(int mode) { int adj; @@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode) /* Signals output enable */ corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); - /* Set Phase Adjuct */ + /* Set Phase Adjust */ lcdtg_set_phadadj(mode); /* Initialize for Input Signals from ATI */ diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index ff6b4ee037f5..40dea3d5142b 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c @@ -32,7 +32,7 @@ static struct corgissp_machinfo *ssp_machinfo; * There are three devices connected to the SSP interface: * 1. A touchscreen controller (TI ADS7846 compatible) * 2. An LCD contoller (with some Backlight functionality) - * 3. A battery moinitoring IC (Maxim MAX1111) + * 3. A battery monitoring IC (Maxim MAX1111) * * Each device uses a different speed/mode of communication. * diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index caf6b8bb6c95..c7bdf04ab094 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -30,7 +30,7 @@ static unsigned long mpcore_timer_rate; /* * local_timer_ack: checks for a local timer interrupt. * - * If a local timer interrupt has occured, acknowledge and return 1. + * If a local timer interrupt has occurred, acknowledge and return 1. * Otherwise, return 0. */ int local_timer_ack(void) diff --git a/arch/arm/mach-s3c2410/bast.h b/arch/arm/mach-s3c2410/bast.h deleted file mode 100644 index e98543742eb9..000000000000 --- a/arch/arm/mach-s3c2410/bast.h +++ /dev/null @@ -1,2 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/bast.h -extern void bast_init_irq(void); diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index bc308ceb91c3..435adcce6482 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -160,7 +160,7 @@ static struct platform_device *amlm5900_devices[] __initdata = { #endif }; -void __init amlm5900_map_io(void) +static void __init amlm5900_map_io(void) { s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); s3c24xx_init_clocks(0); diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 5ccd0be23a33..5c9bcea74767 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -17,6 +17,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 9cc4253d7bbc..d86e6f18bac9 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -27,6 +27,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/sysdev.h> #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/spi/spi.h> diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index d0f4695c09d9..668cccefe7b0 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -59,8 +59,8 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { [DMACH_SPI1] = { .name = "spi1", .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, + .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT, }, [DMACH_UART0] = { .name = "uart0", diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index aafe0bc593f1..782b5814ced2 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -16,6 +16,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/delay.h> #include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -29,6 +30,7 @@ #include <asm/io.h> #include <asm/irq.h> +#include <asm/arch/reset.h> #include <asm/arch/idle.h> #include <asm/arch/regs-clock.h> @@ -37,6 +39,8 @@ #include <asm/arch/regs-gpio.h> #include <asm/arch/regs-gpioj.h> #include <asm/arch/regs-dsc.h> +#include <asm/arch/regs-spi.h> +#include <asm/arch/regs-s3c2412.h> #include <asm/plat-s3c24xx/s3c2412.h> #include <asm/plat-s3c24xx/cpu.h> @@ -74,6 +78,14 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c_device_sdi.name = "s3c2412-sdi"; s3c_device_lcd.name = "s3c2412-lcd"; s3c_device_nand.name = "s3c2412-nand"; + + /* spi channel related changes, s3c2412/13 specific */ + s3c_device_spi0.name = "s3c2412-spi"; + s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24; + s3c_device_spi1.name = "s3c2412-spi"; + s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1; + s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24; + } /* s3c2412_idle @@ -97,6 +109,23 @@ static void s3c2412_idle(void) cpu_do_idle(); } +static void s3c2412_hard_reset(void) +{ + /* errata "Watch-dog/Software Reset Problem" specifies that + * this reset must be done with the SYSCLK sourced from + * EXTCLK instead of FOUT to avoid a glitch in the reset + * mechanism. + * + * See the watchdog section of the S3C2412 manual for more + * information on this fix. + */ + + __raw_writel(0x00, S3C2412_CLKSRC); + __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST); + + mdelay(1); +} + /* s3c2412_map_io * * register the standard cpu IO areas, and any passed in from the @@ -113,6 +142,10 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) s3c24xx_idle = s3c2412_idle; + /* set custom reset hook */ + + s3c24xx_reset_hook = s3c2412_hard_reset; + /* register our io-tables */ iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 324f5a237921..4d6c7a574c1a 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -45,7 +45,7 @@ #include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/cpu.h> -/* onboard perihpheral map */ +/* onboard perihperal map */ static struct map_desc osiris_iodesc[] __initdata = { /* ISA IO areas (may be over-written later) */ diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index c3cc4bf158f6..866ff71c01dd 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -19,6 +19,7 @@ #include <linux/init.h> #include <linux/tty.h> #include <linux/console.h> +#include <linux/sysdev.h> #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/serial.h> diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 0b6e360aeae7..58402948c47c 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -394,7 +394,7 @@ static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate) return 0; } -struct clk clk_usb_bus_host = { +static struct clk clk_usb_bus_host = { .name = "usb-bus-host-parent", .id = -1, .parent = &clk_esysclk, @@ -747,6 +747,24 @@ static struct clk init_clocks[] = { .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_USBD, }, { + .name = "hsmmc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_HSMMC, + }, { + .name = "cfc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_CFC, + }, { + .name = "ssmc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_SSMC, + }, { .name = "timers", .id = -1, .parent = &clk_p, @@ -791,7 +809,8 @@ static struct clk init_clocks[] = { .name = "usb-bus-host", .id = -1, .parent = &clk_usb_bus_host, - }, { .name = "ac97", + }, { + .name = "ac97", .id = -1, .parent = &clk_p, .ctrlbit = S3C2443_PCLKCON_AC97, diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index b71ee53c2865..b1eb709ee65a 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -104,6 +104,7 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = { static struct platform_device *smdk2443_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c, + &s3c_device_hsmmc, }; static void __init smdk2443_map_io(void) diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index 11b1d0b310c3..8d8117158d23 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -63,6 +63,10 @@ int __init s3c2443_init(void) s3c_device_nand.name = "s3c2412-nand"; + /* change WDT IRQ number */ + s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; + s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT; + return sysdev_register(&s3c2443_sysdev); } diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index d7c038a0256b..4cbf9468f654 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -139,12 +139,12 @@ static u_int neponset_get_mctrl(struct uart_port *port) return ret; } -static struct sa1100_port_fns neponset_port_fns __initdata = { +static struct sa1100_port_fns neponset_port_fns __devinitdata = { .set_mctrl = neponset_set_mctrl, .get_mctrl = neponset_get_mctrl, }; -static int neponset_probe(struct platform_device *dev) +static int __devinit neponset_probe(struct platform_device *dev) { sa1100_register_uart_fns(&neponset_port_fns); diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 416e277054c2..29cb0c1604ab 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void) { /* * According to the manual we should be able to let RTTR be zero - * and then a default diviser for a 32.768KHz clock is used. + * and then a default divisor for a 32.768KHz clock is used. * Apparently this doesn't work, at least for my SA1110 rev 5. * If the clock divider is uninitialized then reset it to the * default value to get the 1Hz clock. diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 15f0284010ca..e7904bc92c73 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -351,6 +351,7 @@ config CPU_V6 select CPU_CACHE_V6 select CPU_CACHE_VIPT select CPU_CP15_MMU + select CPU_HAS_ASID select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU @@ -376,8 +377,9 @@ config CPU_V7 select CPU_CACHE_V7 select CPU_CACHE_VIPT select CPU_CP15_MMU + select CPU_HAS_ASID select CPU_COPY_V6 if MMU - select CPU_TLB_V6 if MMU + select CPU_TLB_V7 if MMU # Figure out what processor architecture version we should be using. # This defines the compiler instruction set which depends on the machine type. @@ -496,8 +498,17 @@ config CPU_TLB_V4WBI config CPU_TLB_V6 bool +config CPU_TLB_V7 + bool + endif +config CPU_HAS_ASID + bool + help + This indicates whether the CPU has the ASID register; used to + tag TLB and possibly cache entries. + config CPU_CP15 bool help diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index b5bd335ff14a..762702765fc3 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o +obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 19ca333240ec..36440c899583 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -3,7 +3,7 @@ * * Copyright (C) 1995 Linus Torvalds * Modifications for ARM processor (c) 1995-2001 Russell King - * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc. + * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc. * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. * Copyright (C) 1996, Cygnus Software Technologies Ltd. * diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index d6167ad4e011..f3ade18862aa 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr) #ifndef CONFIG_SMP /* * If this is a section based mapping we need to handle it - * specially as the VM subysystem does not know how to handle + * specially as the VM subsystem does not know how to handle * such a beast. We need the lock here b/c we need to clear * all the mappings before the area can be reclaimed * by someone else. diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 2c4c2422cd1e..2728b0e7d2bb 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -5,7 +5,7 @@ #include <linux/mm.h> #include <linux/mman.h> #include <linux/shm.h> - +#include <linux/sched.h> #include <asm/system.h> #define COLOUR_ALIGN(addr,pgoff) \ diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 2ba1530d1ce1..02e050ae59f6 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = { }; /* - * These are useful for identifing cache coherency + * These are useful for identifying cache coherency * problems by allowing the cache or the cache and * writebuffer to be turned off. (Note: the write * buffer should not be on and the cache off). diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index dd823dd4a374..718f4782ee8b 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -256,7 +256,7 @@ __v7_proc_info: .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP .long cpu_v7_name .long v7_processor_functions - .long v6wbi_tlb_fns + .long v7wbi_tlb_fns .long v6_user_fns .long v7_cache_fns .size __v7_proc_info, . - __v7_proc_info diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S new file mode 100644 index 000000000000..b56dda8052f7 --- /dev/null +++ b/arch/arm/mm/tlb-v7.S @@ -0,0 +1,88 @@ +/* + * linux/arch/arm/mm/tlb-v7.S + * + * Copyright (C) 1997-2002 Russell King + * Modified for ARMv7 by Catalin Marinas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ARM architecture version 6 TLB handling functions. + * These assume a split I/D TLB. + */ +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/page.h> +#include <asm/tlbflush.h> +#include "proc-macros.S" + +/* + * v7wbi_flush_user_tlb_range(start, end, vma) + * + * Invalidate a range of TLB entries in the specified address space. + * + * - start - start address (may not be aligned) + * - end - end address (exclusive, may not be aligned) + * - vma - vma_struct describing address range + * + * It is assumed that: + * - the "Invalidate single entry" instruction will invalidate + * both the I and the D TLBs on Harvard-style TLBs + */ +ENTRY(v7wbi_flush_user_tlb_range) + vma_vm_mm r3, r2 @ get vma->vm_mm + mmid r3, r3 @ get vm_mm->context.id + dsb + mov r0, r0, lsr #PAGE_SHIFT @ align address + mov r1, r1, lsr #PAGE_SHIFT + asid r3, r3 @ mask ASID + orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA + mov r1, r1, lsl #PAGE_SHIFT + vma_vm_flags r2, r2 @ get vma->vm_flags +1: + mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) + tst r2, #VM_EXEC @ Executable area ? + mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) + add r0, r0, #PAGE_SZ + cmp r0, r1 + blo 1b + mov ip, #0 + mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB + dsb + mov pc, lr + +/* + * v7wbi_flush_kern_tlb_range(start,end) + * + * Invalidate a range of kernel TLB entries + * + * - start - start address (may not be aligned) + * - end - end address (exclusive, may not be aligned) + */ +ENTRY(v7wbi_flush_kern_tlb_range) + dsb + mov r0, r0, lsr #PAGE_SHIFT @ align address + mov r1, r1, lsr #PAGE_SHIFT + mov r0, r0, lsl #PAGE_SHIFT + mov r1, r1, lsl #PAGE_SHIFT +1: + mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA + mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA + add r0, r0, #PAGE_SZ + cmp r0, r1 + blo 1b + mov r2, #0 + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB + dsb + isb + mov pc, lr + + .section ".text.init", #alloc, #execinstr + + .type v7wbi_tlb_fns, #object +ENTRY(v7wbi_tlb_fns) + .long v7wbi_flush_user_tlb_range + .long v7wbi_flush_kern_tlb_range + .long v6wbi_tlb_flags + .size v7wbi_tlb_fns, . - v7wbi_tlb_fns diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h index 0a3067452cd2..260fe29d73f5 100644 --- a/arch/arm/nwfpe/softfloat.h +++ b/arch/arm/nwfpe/softfloat.h @@ -273,4 +273,7 @@ static inline flag float64_lt_nocheck(float64 a, float64 b) extern flag float32_is_nan( float32 a ); extern flag float64_is_nan( float64 a ); +extern int32 float64_to_uint32( struct roundingData *roundData, float64 a ); +extern int32 float64_to_uint32_round_to_zero( float64 a ); + #endif diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c index 898500718249..7791da791f5f 100644 --- a/arch/arm/oprofile/op_model_mpcore.c +++ b/arch/arm/oprofile/op_model_mpcore.c @@ -257,8 +257,13 @@ static void em_stop(void) */ static void em_route_irq(int irq, unsigned int cpu) { - irq_desc[irq].affinity = cpumask_of_cpu(cpu); - irq_desc[irq].chip->set_affinity(irq, cpumask_of_cpu(cpu)); + struct irq_desc *desc = irq_desc + irq; + cpumask_t mask = cpumask_of_cpu(cpu); + + spin_lock_irq(&desc->lock); + desc->affinity = mask; + desc->chip->set_affinity(irq, mask); + spin_unlock_irq(&desc->lock); } static int em_setup(void) diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index e2744b7227c5..2b5aa1135b11 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -19,6 +19,7 @@ #include <linux/ioport.h> #include <asm/io.h> #include <asm/irq.h> +#include <asm/signal.h> #include <asm/system.h> #include <asm/hardware.h> #include <asm/mach/pci.h> @@ -85,10 +86,10 @@ static int iop3xx_pci_status(void) /* * Simply write the address register and read the configuration - * data. Note that the 4 nop's ensure that we are able to handle + * data. Note that the 4 nops ensure that we are able to handle * a delayed abort (in theory.) */ -static inline u32 iop3xx_read(unsigned long addr) +static u32 iop3xx_read(unsigned long addr) { u32 val; @@ -321,7 +322,7 @@ void __init iop3xx_atu_disable(void) /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ int init_atu; -void iop3xx_pci_preinit(void) +void __init iop3xx_pci_preinit(void) { if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { iop3xx_atu_disable(); diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index dd8708ad0a71..7987aa6e95f8 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -73,7 +73,7 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) } if (info != NULL) { /* Check the length as a lame attempt to check for - * binary inconsistancy. */ + * binary inconsistency. */ if (len != NO_LENGTH_CHECK) { /* Word-align len */ if (len & 0x03) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 55a4d3be16b6..88d5b6d9f950 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1172,7 +1172,7 @@ static void set_b1_regs(void) break; default: BUG(); - return; /* Supress warning about uninitialized vars */ + return; /* Suppress warning about uninitialized vars */ } if (omap_dma_in_1510_mode()) { diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index bc46f33aede3..1f23f0459e5f 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -59,8 +59,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, /* * Depending on the target RAMFS firewall setup, the public usable amount of - * SRAM varies. The default accessable size for all device types is 2k. A GP - * device allows ARM11 but not other initators for full size. This + * SRAM varies. The default accessible size for all device types is 2k. A GP + * device allows ARM11 but not other initiators for full size. This * functionality seems ok until some nice security API happens. */ static int is_sram_locked(void) @@ -71,7 +71,7 @@ static int is_sram_locked(void) type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; if (type == GP_DEVICE) { - /* RAMFW: R/W access to all initators for all qualifier sets */ + /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index 25489aafb113..a5aedf964b88 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -177,7 +177,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) /* NOTE: SPEED and SUSP aren't configured here. OTG hosts * may be able to use I2C requests to set those bits along - * with VBUS switching and overcurrent detction. + * with VBUS switching and overcurrent detection. */ if (cpu_class_is_omap1() && nwires != 6) diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 908efa7d745f..7ed19b23ce56 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -18,6 +18,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/sysdev.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> @@ -29,6 +30,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <asm/mach-types.h> #include <asm/hardware.h> #include <asm/io.h> #include <asm/irq.h> @@ -192,6 +194,9 @@ void __init smdk_machine_init(void) s3c2410_gpio_setpin(S3C2410_GPF6, 1); s3c2410_gpio_setpin(S3C2410_GPF7, 1); + if (machine_is_smdk2443()) + smdk_nand_info.twrph0 = 50; + s3c_device_nand.dev.platform_data = &smdk_nand_info; platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 0fe53b39cb2f..5875da0ae0eb 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -33,6 +33,7 @@ #include <asm/plat-s3c24xx/devs.h> #include <asm/plat-s3c24xx/cpu.h> +#include <asm/arch/regs-spi.h> /* Serial port registrations */ @@ -402,6 +403,36 @@ struct platform_device s3c_device_sdi = { EXPORT_SYMBOL(s3c_device_sdi); +/* High-speed MMC/SD */ + +static struct resource s3c_hsmmc_resource[] = { + [0] = { + .start = S3C2443_PA_HSMMC, + .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3C2443_HSMMC, + .end = IRQ_S3C2443_HSMMC, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_hsmmc = { + .name = "s3c-sdhci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), + .resource = s3c_hsmmc_resource, + .dev = { + .dma_mask = &s3c_device_hsmmc_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + + + /* SPI (0) */ static struct resource s3c_spi0_resource[] = { @@ -437,8 +468,8 @@ EXPORT_SYMBOL(s3c_device_spi0); static struct resource s3c_spi1_resource[] = { [0] = { - .start = S3C24XX_PA_SPI + 0x20, - .end = S3C24XX_PA_SPI + 0x20 + 0x1f, + .start = S3C24XX_PA_SPI + S3C2410_SPI1, + .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 6f03c9370979..08d80f2f51f2 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1153,7 +1153,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); * * hwcfg: the value for xxxSTCn register, * bit 0: 0=increment pointer, 1=leave pointer - * bit 1: 0=soucre is AHB, 1=soucre is APB + * bit 1: 0=source is AHB, 1=source is APB * * devaddr: physical address of the source */ diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index bd965f2feeca..cb0b3a4ccf1b 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c @@ -18,6 +18,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/sysdev.h> #include <linux/device.h> #include <asm/mach/arch.h> diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index c6b03f8ab260..5692eccdf4d1 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c @@ -555,7 +555,7 @@ static int s3c2410_pm_enter(suspend_state_t state) __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - /* call cpu specific preperation */ + /* call cpu specific preparation */ pm_cpu_prep(); |