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| author | Vladimir Murzin <vladimir.murzin@arm.com> | 2016-11-02 14:54:06 +0300 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-11-29 12:14:48 +0300 |
| commit | 0968a61918a9140d39959a318f796412354ec24d (patch) | |
| tree | a1283ec6f25af67f03d48913cc9d3be99ce3ec65 /arch/arm64/include/asm/arch_gicv3.h | |
| parent | 328191c05ed72762c382bdb835607dd5bd56b0bc (diff) | |
| download | linux-0968a61918a9140d39959a318f796412354ec24d.tar.xz | |
irqchip/gic-v3-its: Specialise readq and writeq accesses
readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/arch_gicv3.h')
| -rw-r--r-- | arch/arm64/include/asm/arch_gicv3.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 546f92b32b62..f37e3a21f6e7 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -174,5 +174,19 @@ static inline void gic_write_bpr1(u32 val) #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) +#define gits_read_baser(c) readq_relaxed(c) +#define gits_write_baser(v, c) writeq_relaxed(v, c) + +#define gits_read_cbaser(c) readq_relaxed(c) +#define gits_write_cbaser(v, c) writeq_relaxed(v, c) + +#define gits_write_cwriter(v, c) writeq_relaxed(v, c) + +#define gicr_read_propbaser(c) readq_relaxed(c) +#define gicr_write_propbaser(v, c) writeq_relaxed(v, c) + +#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c) +#define gicr_read_pendbaser(c) readq_relaxed(c) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_GICV3_H */ |