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| author | Nishanth Menon <nm@ti.com> | 2022-02-15 23:10:05 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-04-08 15:22:58 +0300 |
| commit | e931b8494a51e5e347f1430eef96339d867962b2 (patch) | |
| tree | 99100ceeb14fd7f5b34797a88e1047a00968e2e5 /arch/arm64/boot/dts/ti/k3-j7200.dtsi | |
| parent | 146ad3e0177d4fb31b552d19a3a8f358943d50f0 (diff) | |
| download | linux-e931b8494a51e5e347f1430eef96339d867962b2.tar.xz | |
arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
commit a06ed27f3bc63ab9e10007dc0118d910908eb045 upstream.
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Cc: stable@vger.kernel.org # 5.10+
Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j7200.dtsi')
0 files changed, 0 insertions, 0 deletions