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| author | Li Yang <leoyang.li@nxp.com> | 2016-06-17 02:35:03 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2016-06-21 09:33:30 +0300 |
| commit | ec049f334872e98332dcf044943f3fa7cea742ee (patch) | |
| tree | 9382908c4db24da99742f5e5db340b75fdcd9327 /arch/arm64/boot/dts/freescale | |
| parent | f8ed1d9b0f6758db7e2b65b6e88f8a923a3a22ab (diff) | |
| download | linux-ec049f334872e98332dcf044943f3fa7cea742ee.tar.xz | |
arm64: dts: ls1043a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index c451b814ac74..19572d85c80d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -65,6 +65,7 @@ compatible = "arm,cortex-a53"; reg = <0x0>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -72,6 +73,7 @@ compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -79,6 +81,7 @@ compatible = "arm,cortex-a53"; reg = <0x2>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -86,6 +89,11 @@ compatible = "arm,cortex-a53"; reg = <0x3>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; }; }; |